Design and implementation of a serial bus with multiple masters and slaves, arbiter and top-level design that can carry out a specific set of tasks, including data transfer, prioritybased and split arbiter transaction & top-level verification.
This repository include the design and the source files of custom serial bus protocol. This protocol uses a centralized bus arbiter to support both internal and external communication.
To see the specifications of design refer to Specifications.md
To see the modules of design refer to modules.md
To know how to use this repo to setup the protocol refer to hows.md
Source files - src files
Testbench files - testbench files
The report of this protocol can be found in Serial Bus Protocol Design