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A tool ROM to detect failures of DRAM chips.
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IPL.ROM | ||
IPL.als |
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ORG $0000 | ||
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; ----------------------------------------------------------------------------- | ||
; Definitions | ||
; ----------- | ||
CHRMAP "DISPLAYCODE-EU" | ||
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; ----------------------------------------------------------------------------- | ||
; Main entry | ||
; ---------- | ||
rom_main: | ||
; No interrupt | ||
DI | ||
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; Draw text background | ||
LD HL,vram_background | ||
LD DE,$D000 | ||
LD BC,1000 | ||
LDIR | ||
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loop: LD HL,$D000 | ||
LD (HL),32 | ||
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LD HL,$E002 | ||
LD A,$7F ; C = ($E002) > $7F <=> $E002.bit7 == 0 | ||
@@: CP (HL) ; poll /VBLK until it becomes low (asserted) | ||
JP C,@b | ||
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LD HL,$D000 | ||
INC (HL) | ||
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; Check DRAM chips in area $1000-$4FFF - DRAM (I) | ||
check_dram_1000_4FFF: | ||
LD C,0 | ||
LD HL,$1000 | ||
@0: LD (HL),$00 | ||
LD A,(HL) | ||
XOR $00 | ||
OR C | ||
LD C,A | ||
LD (HL),$55 | ||
LD A,(HL) | ||
XOR $55 | ||
OR C | ||
LD C,A | ||
LD (HL),$AA | ||
LD A,(HL) | ||
XOR $AA | ||
OR C | ||
LD C,A | ||
LD (HL),$FF | ||
LD A,(HL) | ||
XOR $FF | ||
OR C | ||
LD C,A | ||
INC L | ||
JR NZ,@0b | ||
INC H | ||
LD A,$50 | ||
CP H | ||
JR NZ,@0b | ||
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LD DE,$476D ; XO | ||
BIT 0,C | ||
LD HL,$D000+(2*40)+34 ; BIT D0 is OK/KO | ||
LD A,D | ||
JR Z,@0f | ||
LD A,E | ||
@0: LD (HL),A | ||
BIT 1,C | ||
LD HL,$D000+(5*40)+34 ; BIT D1 is OK/KO | ||
LD A,D | ||
JR Z,@1f | ||
LD A,E | ||
@1: LD (HL),A | ||
BIT 2,C | ||
LD HL,$D000+(8*40)+34 ; BIT D2 is OK/KO | ||
LD A,D | ||
JR Z,@2f | ||
LD A,E | ||
@2: LD (HL),A | ||
BIT 3,C | ||
LD HL,$D000+(11*40)+34 ; BIT D3 is OK/KO | ||
LD A,D | ||
JR Z,@3f | ||
LD A,E | ||
@3: LD (HL),A | ||
BIT 4,C | ||
LD B,$C1 | ||
LD HL,$D000+(14*40)+34 ; BIT D4 is OK/KO | ||
LD A,D | ||
JR Z,@4f | ||
LD A,E | ||
@4: LD (HL),A | ||
BIT 5,C | ||
LD HL,$D000+(17*40)+34 ; BIT D5 is OK/KO | ||
LD A,D | ||
JR Z,@5f | ||
LD A,E | ||
@5: LD (HL),A | ||
BIT 6,C | ||
LD HL,$D000+(20*40)+34 ; BIT D6 is OK/KO | ||
LD A,D | ||
JR Z,@6f | ||
LD A,E | ||
@6: LD (HL),A | ||
BIT 7,C | ||
LD HL,$D000+(23*40)+34 ; BIT D7 is OK/KO | ||
LD A,D | ||
JR Z,@7f | ||
LD A,E | ||
@7: LD (HL),A | ||
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LD HL,$D000 | ||
INC (HL) | ||
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; Check DRAM chips in area $5000-$9FFF - DRAM (II) | ||
check_dram_5000_9FFF: | ||
LD C,0 | ||
LD HL,$5000 | ||
@0: LD (HL),$00 | ||
LD A,(HL) | ||
XOR $00 | ||
OR C | ||
LD C,A | ||
LD (HL),$55 | ||
LD A,(HL) | ||
XOR $55 | ||
OR C | ||
LD C,A | ||
LD (HL),$AA | ||
LD A,(HL) | ||
XOR $AA | ||
OR C | ||
LD C,A | ||
LD (HL),$FF | ||
LD A,(HL) | ||
XOR $FF | ||
OR C | ||
LD C,A | ||
INC L | ||
JR NZ,@0b | ||
INC H | ||
LD A,$A0 | ||
CP H | ||
JR NZ,@0b | ||
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LD DE,$476D ; XO | ||
BIT 0,C | ||
LD HL,$D000+(2*40)+23 ; BIT D0 is OK/KO | ||
LD A,D | ||
JR Z,@0f | ||
LD A,E | ||
@0: LD (HL),A | ||
BIT 1,C | ||
LD HL,$D000+(5*40)+23 ; BIT D1 is OK/KO | ||
LD A,D | ||
JR Z,@1f | ||
LD A,E | ||
@1: LD (HL),A | ||
BIT 2,C | ||
LD HL,$D000+(8*40)+23 ; BIT D2 is OK/KO | ||
LD A,D | ||
JR Z,@2f | ||
LD A,E | ||
@2: LD (HL),A | ||
BIT 3,C | ||
LD HL,$D000+(11*40)+23 ; BIT D3 is OK/KO | ||
LD A,D | ||
JR Z,@3f | ||
LD A,E | ||
@3: LD (HL),A | ||
BIT 4,C | ||
LD B,$C1 | ||
LD HL,$D000+(14*40)+23 ; BIT D4 is OK/KO | ||
LD A,D | ||
JR Z,@4f | ||
LD A,E | ||
@4: LD (HL),A | ||
BIT 5,C | ||
LD HL,$D000+(17*40)+23 ; BIT D5 is OK/KO | ||
LD A,D | ||
JR Z,@5f | ||
LD A,E | ||
@5: LD (HL),A | ||
BIT 6,C | ||
LD HL,$D000+(20*40)+23 ; BIT D6 is OK/KO | ||
LD A,D | ||
JR Z,@6f | ||
LD A,E | ||
@6: LD (HL),A | ||
BIT 7,C | ||
LD HL,$D000+(23*40)+23 ; BIT D7 is OK/KO | ||
LD A,D | ||
JR Z,@7f | ||
LD A,E | ||
@7: LD (HL),A | ||
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LD HL,$D000 | ||
INC (HL) | ||
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; Check DRAM chips in area $A000-$CFFF - DRAM (III) | ||
check_dram_A000_CFFF: | ||
LD C,0 | ||
LD HL,$A000 | ||
@0: LD (HL),$00 | ||
LD A,(HL) | ||
XOR $00 | ||
OR C | ||
LD C,A | ||
LD (HL),$55 | ||
LD A,(HL) | ||
XOR $55 | ||
OR C | ||
LD C,A | ||
LD (HL),$AA | ||
LD A,(HL) | ||
XOR $AA | ||
OR C | ||
LD C,A | ||
LD (HL),$FF | ||
LD A,(HL) | ||
XOR $FF | ||
OR C | ||
LD C,A | ||
INC L | ||
JR NZ,@0b | ||
INC H | ||
LD A,$D0 | ||
CP H | ||
JR NZ,@0b | ||
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LD DE,$476D ; XO | ||
BIT 0,C | ||
LD HL,$D000+(2*40)+11 ; BIT D0 is OK/KO | ||
LD A,D | ||
JR Z,@0f | ||
LD A,E | ||
@0: LD (HL),A | ||
BIT 1,C | ||
LD HL,$D000+(5*40)+11 ; BIT D1 is OK/KO | ||
LD A,D | ||
JR Z,@1f | ||
LD A,E | ||
@1: LD (HL),A | ||
BIT 2,C | ||
LD HL,$D000+(8*40)+11 ; BIT D2 is OK/KO | ||
LD A,D | ||
JR Z,@2f | ||
LD A,E | ||
@2: LD (HL),A | ||
BIT 3,C | ||
LD HL,$D000+(11*40)+11 ; BIT D3 is OK/KO | ||
LD A,D | ||
JR Z,@3f | ||
LD A,E | ||
@3: LD (HL),A | ||
BIT 4,C | ||
LD B,$C1 | ||
LD HL,$D000+(14*40)+11 ; BIT D4 is OK/KO | ||
LD A,D | ||
JR Z,@4f | ||
LD A,E | ||
@4: LD (HL),A | ||
BIT 5,C | ||
LD HL,$D000+(17*40)+11 ; BIT D5 is OK/KO | ||
LD A,D | ||
JR Z,@5f | ||
LD A,E | ||
@5: LD (HL),A | ||
BIT 6,C | ||
LD HL,$D000+(20*40)+11 ; BIT D6 is OK/KO | ||
LD A,D | ||
JR Z,@6f | ||
LD A,E | ||
@6: LD (HL),A | ||
BIT 7,C | ||
LD HL,$D000+(23*40)+11 ; BIT D7 is OK/KO | ||
LD A,D | ||
JR Z,@7f | ||
LD A,E | ||
@7: LD (HL),A | ||
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JP loop | ||
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vram_background: | ||
DB $00,$79,$00,$04,$12,$01,$0D,$00,$68,$09,$09,$09,$69,$00,$00,$04,$12,$01,$0D,$00,$00,$68,$09,$09,$69,$00,$00,$04,$12,$01,$0D,$00,$00,$68,$09,$69,$00,$00,$00,$00 | ||
DB $78,$6E,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $43,$31,$79,$00,$63,$21,$27,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$29,$00,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$00,$00,$00,$00,$49,$00,$1E,$04,$20,$00 | ||
DB $43,$31,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $43,$31,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $43,$31,$79,$00,$63,$21,$28,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$20,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$22,$00,$00,$00,$00,$49,$00,$1E,$04,$21,$00 | ||
DB $43,$31,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $43,$31,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $43,$31,$79,$00,$63,$21,$29,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$21,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$23,$00,$00,$00,$00,$49,$00,$1E,$04,$22,$00 | ||
DB $43,$31,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $43,$31,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $43,$31,$79,$00,$63,$22,$20,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$22,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$24,$00,$00,$00,$00,$49,$00,$1E,$04,$23,$00 | ||
DB $43,$31,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $43,$31,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $34,$4C,$79,$00,$63,$22,$21,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$23,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$25,$00,$00,$00,$00,$49,$00,$1E,$04,$24,$00 | ||
DB $47,$79,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $00,$5E,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $0F,$79,$79,$00,$63,$22,$22,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$24,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$26,$00,$00,$00,$00,$49,$00,$1E,$04,$25,$00 | ||
DB $0B,$79,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $78,$5E,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $6D,$79,$79,$00,$63,$22,$23,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$25,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$27,$00,$00,$00,$00,$49,$00,$1E,$04,$26,$00 | ||
DB $00,$5E,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
DB $0B,$79,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$5C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$5D,$00,$00,$00 | ||
DB $0F,$79,$79,$00,$63,$22,$24,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$21,$26,$00,$00,$00,$00,$49,$00,$1E,$5E,$00,$63,$28,$00,$00,$00,$00,$49,$00,$1E,$04,$27,$00 | ||
DB $78,$6E,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$1C,$78,$78,$78,$78,$78,$78,$78,$78,$78,$1D,$00,$00,$00 | ||
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DS $1000 - $ | ||
; ----------------------------------------------------------------------------- | ||
END rom_main |
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cd exe | ||
build_exe.bat |
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cd .. | ||
exe\z80as.exe -x -o IPL.ROM DRAMTester.a80 | ||
pause |
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