automated update

57738fc [sim/tut3_pymtl] finish code for tut

.changelog

@@ -1,3 +1,4 @@
+57738fc [sim/tut3_pymtl] finish code for tut
 7b636e0 remove unwanted subdirs from tut
 2a7f307 [sim/tut3_pymtl] first attempt at new code approach
 7388211 update README for tut3

sim/tut3_pymtl/regincr/RegIncr.py

@@ -29,15 +29,10 @@ def block1():
       else:
         s.reg_out.next = s.in_
 
-    # Concurrent block modeling incrementer
-
-    # ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
-    # Use a combinational concurrent block to model the incrementer
-    # logic. Remember to always use .value when writing signals from
-    # within a combinational concurrent block!
-
-  # Line Tracing
-
-  def line_trace( s ):
-    return "{} ({}) {}".format( s.in_, s.reg_out, s.out )
+    # ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''''
+    # This model is incomplete. As part of the tutorial you will add a
+    # combinational concurrent block to model the incrementer logic, and
+    # later you will a line tracing function to compactly output the
+    # input, register, and output vaules.
+    # '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 

sim/tut3_pymtl/regincr/RegIncr2stage.py

@@ -25,12 +25,11 @@ def __init__( s ):
 
     s.connect( s.in_, s.reg_incr_0.in_ )
 
-    # Second stage
-
-    s.reg_incr_1 = RegIncr()
-
-    s.connect( s.reg_incr_0.out, s.reg_incr_1.in_ )
-    s.connect( s.reg_incr_1.out, s.out )
+    # ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
+    # This model is incomplete. As part of the tutorial you will add code
+    # to connect the second stage of this two-stage registered
+    # incrementer.
+    # ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
   # Line Tracing
 

sim/tut3_pymtl/regincr/RegIncrNstage.py

@@ -25,10 +25,10 @@ def __init__( s, nstages=2 ):
 
     s.connect( s.in_, s.reg_incrs[0].in_ )
 
-    # Connect reg_incr in chain
-
-    for i in xrange( nstages - 1 ):
-      s.connect( s.reg_incrs[i].out, s.reg_incrs[i+1].in_ )
+    # ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
+    # This model is incomplete. As part of the tutorial you will add code
+    # to connect the stages together.
+    # ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
     # Connect last reg_incr in chain to output port
 

sim/tut3_pymtl/regincr/RegIncr_extra_test.py

@@ -34,31 +34,9 @@ def test_large( dump_vcd ):
     [ 0x00, 0xc7 ],
   ], dump_vcd )
 
-#-------------------------------------------------------------------------
-# test_overflow
-#-------------------------------------------------------------------------
-
-def test_overflow( dump_vcd ):
-  run_test_vector_sim( RegIncr(), [
-    ('in_   out*'),
-    [ 0x00, '?'  ],
-    [ 0xfe, 0x01 ],
-    [ 0xff, 0xff ],
-    [ 0x00, 0x00 ],
-  ], dump_vcd )
-
-#-------------------------------------------------------------------------
-# test_random
-#-------------------------------------------------------------------------
-
-def test_random( dump_vcd ):
-
-  test_vector_table = [( 'in_', 'out*' )]
-  last_result = '?'
-  for i in xrange(20):
-    rand_value = Bits( 8, random.randint(0,0xff) )
-    test_vector_table.append( [ rand_value, last_result ] )
-    last_result = Bits( 8, rand_value + 1 )
-
-  run_test_vector_sim( RegIncr(), test_vector_table, dump_vcd )
+# ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''''''''
+# This test script is incomplete. As part of the tutorial you will add
+# another test case to test for overflow. Later you will add a test case
+# for random testing.
+# '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 

sim/tut3_pymtl/regincr/RegIncr_test.py

@@ -49,12 +49,9 @@ def t( in_, out ):
 
     sim.cycle()
 
-  # Cycle-by-cycle tests
-
-  t( 0x00, '?'  )
-  t( 0x13, 0x01 )
-  t( 0x27, 0x14 )
-  t( 0x00, 0x28 )
-  t( 0x00, 0x01 )
-  t( 0x00, 0x01 )
+  # ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''''''
+  # This test script is incomplete. As part of the tutorial you will add
+  # a sequence of test cases to set the input and verify the output of
+  # the registered incrementer.
+  # '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 

sim/tut3_pymtl/regincr/regincr-sim

@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #=========================================================================
-# regincr-sim-v2 <input-values>
+# regincr-sim <input-values>
 #=========================================================================
 
 from pymtl   import *
@@ -15,15 +15,12 @@ input_values = [ int(x,0) for x in argv[1:] ]
 
 input_values.extend( [0]*3 )
 
-# Elaborate the model
-
-model = RegIncr()
-model.vcd_file = "regincr-sim.vcd"
-model.elaborate()
-
-# Create a simulator using simulation tool
-
-sim = SimulationTool( model )
+# ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''''''
+# This simulator script is incomplete. As part of the tutorial you will
+# need to add the code for constructing and elaborating a RegIncr model
+# before using the SimulationTool to create a simulator. Later in the
+# tutorial you will nee to add a line to enable VCD dumping.
+# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
 # Reset simulator
 
@@ -37,9 +34,14 @@ for input_value in input_values:
 
   model.in_.value = input_value
 
-  # Display line trace
+  # ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''''
+  # In the following print statement we are directly using the model
+  # ports to create some tracing output. Later in the tutorial you will
+  # replace this with a call to the simulator's print_line_trace method.
+  # ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-  sim.print_line_trace()
+  print " cycle = {}: in = {}, out = {}" \
+    .format( sim.ncycles, model.in_, model.out )
 
   # Tick simulator one cycle