add timestamp640, pulse_gen640

basil/HL/pulse_gen640.py

@@ -0,0 +1,98 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer
+
+
+class pulse_gen640(RegisterHardwareLayer):
+    '''Pulser generator
+    '''
+
+    _registers = {'RESET': {'descr': {'addr': 0, 'size': 8, 'properties': ['writeonly']}},
+                  'VERSION': {'descr': {'addr': 0, 'size': 8, 'properties': ['ro']}},
+                  'READY': {'descr': {'addr': 1, 'size': 1, 'properties': ['ro']}},
+                  'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}},
+                  'EN': {'descr': {'addr': 2, 'size': 1}},
+                  'DELAY': {'descr': {'addr': 3, 'size': 32}},
+                  'WIDTH': {'descr': {'addr': 7, 'size': 32}},
+                  'REPEAT': {'descr': {'addr': 11, 'size': 32}},
+                  'PHASE_DES': {'descr': {'addr': 15, 'size': 16}},
+                  'DEBUG': {'descr': {'addr': 17, 'size': 64}},
+                  }
+    _require_version = "==1"
+
+    def __init__(self, intf, conf):
+        super(pulse_gen640, self).__init__(intf, conf)
+
+    def start(self):
+        '''
+        Software start of pulse at random time
+        '''
+        self.START = 0
+
+    def reset(self):
+        self.RESET = 0
+
+    def set_delay(self, value):
+        '''
+        Pulse delay w.r.t. shift register finish signal [in clock cycles(?)]
+        '''
+        self.DELAY = value
+
+    def get_delay(self):
+        return self.DELAY
+
+    def set_phase(self, value):
+        '''
+        Pulse phase in 640MHz from 0 to 16
+        '''
+        self.PHASE_DES = (0xFFFF << (value % 16)) & 0xFFFF
+
+    def get_phase(self):
+        # print("=====sim=====", self.PHASE_DES, self.DELAY)
+        for i in range(16):
+            if ((0xFFFF0000 | self.PHASE_DES) >> i) & 0xFFFF == 0xFFFF:
+                break
+        return i
+
+    def set_width(self, value):
+        '''
+        Pulse width in terms of clock cycles
+        '''
+        self.WIDTH = value
+
+    def get_width(self):
+        return self.WIDTH
+
+    def set_repeat(self, value):
+        '''
+        Pulse repetition in range of 0-255
+        '''
+        self.REPEAT = value
+
+    def get_repeat(self):
+        return self.REPEAT
+
+    def is_done(self):
+        return self.is_ready
+
+    @property
+    def is_ready(self):
+        return self.READY
+
+    def set_en(self, value):
+        '''
+        If true: The pulse comes with a fixed delay with respect to the external trigger (EXT_START).
+        If false: The pulse comes only at software start.
+        '''
+        self.EN = value
+
+    def get_en(self):
+        '''
+        Return info if pulse starts with a fixed delay w.r.t. shift register finish signal (true) or if it only starts with .start() (false)
+        '''
+        return self.EN

basil/HL/timestamp640.py

@@ -0,0 +1,34 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer
+
+
+class timestamp640(RegisterHardwareLayer):
+    '''Implement timestamp driver.
+    '''
+
+    def __init__(self, intf, conf):
+        self._registers = {'RESET': {'descr': {'addr': 0, 'size': 8, 'properties': ['writeonly']}},
+                           'VERSION': {'descr': {'addr': 0, 'size': 8, 'properties': ['ro']}},
+                           'ENABLE': {'descr': {'addr': 2, 'size': 1, 'offset': 0}},
+                           'EXT_TIMESTAMP': {'descr': {'addr': 2, 'size': 1, 'offset': 1}},
+                           'ENABLE_EXTERN': {'descr': {'addr': 2, 'size': 1, 'offset': 2}},
+                           'ENABLE_TRAILING': {'descr': {'addr': 2, 'size': 1, 'offset': 3}},
+                           'INVERT': {'descr': {'addr': 2, 'size': 1, 'offset': 4}},
+                           'LOST_COUNT': {'descr': {'addr': 3, 'size': 8}},
+                           }
+        self._require_version = "==3"
+
+        super(timestamp640, self).__init__(intf, conf)
+
+    def init(self):
+        super(timestamp640, self).init()
+
+    def reset(self):
+        '''Soft reset the module.'''
+        self.RESET = 0

basil/firmware/modules/pulse_gen640/README.rst

@@ -0,0 +1,45 @@
+
+===============================
+**pulse_gen** - pulse generator
+===============================
+
+Simple pulse generator with configurable delay and width.
+
+**Unit test/Example:** 
+`test_SimTimestamp640.v <https://github.com/SiLab-Bonn/basil/blob/master/tests/test_SimTimestamp640.v>`_ 
+`test_SimTimestamp40.py <https://github.com/SiLab-Bonn/basil/blob/master/tests/test_SimTimestamp640.py>`_
+
+Pins
+    +---------------+---------------------+-----------------------+------------------------------------------------------+ 
+    | Name          | Size                | Direction             | Description                                          | 
+    +===============+=====================+=======================+======================================================+ 
+    | EXT_START     | 1                   |  input                | active high start signal (synchronous to PULSE_CLK)  | 
+    +---------------+---------------------+-----------------------+------------------------------------------------------+ 
+    | PULSE_CLK     | 1                   |  input                | module clock                                         | 
+    +---------------+---------------------+-----------------------+------------------------------------------------------+ 
+    | PULSE_CLK160  | 1                   |  input                | module clock (4xPULSE_CLK)                           | 
+    +---------------+---------------------+-----------------------+------------------------------------------------------+ 
+    | PULSE_CLK320  | 1                   |  input                | module clock (8xPULSE_CLK)                           | 
+    +---------------+---------------------+-----------------------+------------------------------------------------------+ 
+    | PULSE         | 1                   |  output               | output pulse                                         | 
+    +---------------+---------------------+-----------------------+------------------------------------------------------+ 
+
+Registers
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | Name          | Address                          | Bits   | r/w   | Default     | Description                                                                                | 
+    +===============+==================================+========+=======+=============+============================================================================================+ 
+    | START         | 1                                |        | wo    |             | software start on write to address                                                         | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | READY         | 1                                | [0]    | ro    | 0           | indicate finish                                                                            | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | EN            | 2                                | [0]    | r/w   | 0           | enable external start                                                                      | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | DELAY         | 6 - 3                            | [31:0] | r/w   | 0           | pulse delay from start                                                                     | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | WIDTH         | 10 - 7                           | [31:0] | r/w   | 0           | pulse width                                                                                | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | REPEAT        | 11 - 14                          | [31:0] | r/w   | 1           | repeat count (0 ->forever)                                                                 | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+    | PHASE_DES     | 15 - 16                          | [15:0] | r/w   | 0           | phase delay (0x0->0, 0x1->1, 0x8000->15)                                                              | 
+    +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ 
+

basil/firmware/modules/pulse_gen640/pulse_gen640.v

@@ -0,0 +1,74 @@
+/**
+ * ------------------------------------------------------------
+ * Copyright (c) All rights reserved 
+ * SiLab, Institute of Physics, University of Bonn
+ * ------------------------------------------------------------
+ */
+`timescale 1ps/1ps
+`default_nettype none
+
+module pulse_gen640
+#(
+    parameter BASEADDR = 16'h0000,
+    parameter HIGHADDR = 16'h0000,
+    parameter ABUSWIDTH = 16,
+    parameter CLKDV = 4,
+    parameter OUTPUT_SIZE =2 
+)(
+    input wire BUS_CLK,
+    input wire [ABUSWIDTH-1:0] BUS_ADD,
+    inout wire [7:0] BUS_DATA,
+    input wire BUS_RST,
+    input wire BUS_WR,
+    input wire BUS_RD,
+
+    input wire  PULSE_CLK,
+    input wire PULSE_CLK160,
+    input wire  PULSE_CLK320,
+    input wire  EXT_START,
+    output wire [OUTPUT_SIZE-1:0] PULSE,
+    output wire DEBUG
+); 
+
+wire IP_RD, IP_WR;
+wire [ABUSWIDTH-1:0] IP_ADD;
+wire [7:0] IP_DATA_IN;
+wire [7:0] IP_DATA_OUT;
+
+bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
+(
+    .BUS_RD(BUS_RD),
+    .BUS_WR(BUS_WR),
+    .BUS_ADD(BUS_ADD),
+    .BUS_DATA(BUS_DATA),
+
+    .IP_RD(IP_RD),
+    .IP_WR(IP_WR),
+    .IP_ADD(IP_ADD),
+    .IP_DATA_IN(IP_DATA_IN),
+    .IP_DATA_OUT(IP_DATA_OUT)
+);
+
+pulse_gen640_core #(
+    .ABUSWIDTH(ABUSWIDTH),
+    .CLKDV(CLKDV),
+    .OUTPUT_SIZE(OUTPUT_SIZE)
+) i_pulse_gen640_core (
+
+    .BUS_CLK(BUS_CLK),
+    .BUS_RST(BUS_RST),
+    .BUS_ADD(IP_ADD),
+    .BUS_DATA_IN(IP_DATA_IN),
+    .BUS_RD(IP_RD),
+    .BUS_WR(IP_WR),
+    .BUS_DATA_OUT(IP_DATA_OUT),
+
+    .PULSE_CLK(PULSE_CLK),
+    .PULSE_CLK160(PULSE_CLK160),
+    .PULSE_CLK320(PULSE_CLK320),
+    .EXT_START(EXT_START),
+    .PULSE(PULSE),
+    .DEBUG(DEBUG)
+);
+
+endmodule