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Naming fix for ff.cc
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@akashlevy
akashlevy committed Nov 21, 2024
1 parent b9456ac commit 08ff023
Showing 1 changed file with 52 additions and 56 deletions.
108 changes: 52 additions & 56 deletions kernel/ff.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -263,11 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva
}

FfData FfData::slice(const std::vector<int> &bits) {
// SILIMATE: Use uniquified ID with $
// TODO: improve this
IdString new_id = IdString("$" + name.str());
while (module->count_id(new_id) > 0) new_id = IdString("$" + new_id.str());
FfData res(module, initvals, new_id);
FfData res(module, initvals, NEW_ID2_SUFFIX("slice")); // SILIMATE: Improve the naming
res.sig_clk = sig_clk;
res.sig_ce = sig_ce;
res.sig_aload = sig_aload;
Expand Down Expand Up @@ -404,21 +400,21 @@ void FfData::aload_to_sr() {
pol_clr = false;
pol_set = true;
if (pol_aload) {
sig_clr = module->Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload);
sig_set = module->Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload);
sig_clr = module->Mux(NEW_ID2_SUFFIX("clr"), Const(State::S1, width), sig_ad, sig_aload, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_set = module->Mux(NEW_ID2_SUFFIX("set"), Const(State::S0, width), sig_ad, sig_aload, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_clr = module->Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload);
sig_set = module->Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload);
sig_clr = module->Mux(NEW_ID2_SUFFIX("clr"), sig_ad, Const(State::S1, width), sig_aload, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_set = module->Mux(NEW_ID2_SUFFIX("set"), sig_ad, Const(State::S0, width), sig_aload, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
pol_clr = pol_aload;
pol_set = pol_aload;
if (pol_aload) {
sig_clr = module->AndnotGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->AndGate(NEW_ID, sig_aload, sig_ad);
sig_clr = module->AndnotGate(NEW_ID2_SUFFIX("clr"), sig_aload, sig_ad, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_set = module->AndGate(NEW_ID2_SUFFIX("set"), sig_aload, sig_ad, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_clr = module->OrGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->OrnotGate(NEW_ID, sig_aload, sig_ad);
sig_clr = module->OrGate(NEW_ID2_SUFFIX("clr"), sig_aload, sig_ad, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_set = module->OrnotGate(NEW_ID2_SUFFIX("set"), sig_aload, sig_ad, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
}
}
Expand All @@ -431,31 +427,31 @@ void FfData::convert_ce_over_srst(bool val) {
if (!is_fine) {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->Or(NEW_ID, sig_ce, sig_srst);
sig_ce = module->Or(NEW_ID2_SUFFIX("ce"), sig_ce, sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->Or(NEW_ID, sig_ce, tmp);
SigSpec tmp = module->Not(NEW_ID2_SUFFIX("tmp"), sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_ce = module->Or(NEW_ID2_SUFFIX("ce"), sig_ce, tmp, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
if (pol_srst) {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->And(NEW_ID, sig_ce, tmp);
SigSpec tmp = module->Not(NEW_ID2_SUFFIX("tmp"), sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_ce = module->And(NEW_ID2_SUFFIX("ce"), sig_ce, tmp, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_ce = module->And(NEW_ID, sig_ce, sig_srst);
sig_ce = module->And(NEW_ID2_SUFFIX("ce"), sig_ce, sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
}
} else {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->OrGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->OrGate(NEW_ID2_SUFFIX("ce"), sig_ce, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_ce = module->OrnotGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->OrnotGate(NEW_ID2_SUFFIX("ce"), sig_ce, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
if (pol_srst) {
sig_ce = module->AndnotGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->AndnotGate(NEW_ID2_SUFFIX("ce"), sig_ce, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_ce = module->AndGate(NEW_ID, sig_ce, sig_srst);
sig_ce = module->AndGate(NEW_ID2_SUFFIX("ce"), sig_ce, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
}
}
Expand All @@ -464,31 +460,31 @@ void FfData::convert_ce_over_srst(bool val) {
if (!is_fine) {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->And(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->And(NEW_ID2_SUFFIX("srst"), sig_srst, sig_ce, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->And(NEW_ID, sig_srst, tmp);
SigSpec tmp = module->Not(NEW_ID2_SUFFIX("tmp"), sig_ce, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_srst = cell->module->And(NEW_ID2_SUFFIX("srst"), sig_srst, tmp, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
if (pol_ce) {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->Or(NEW_ID, sig_srst, tmp);
SigSpec tmp = module->Not(NEW_ID2_SUFFIX("tmp"), sig_ce, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
sig_srst = cell->module->Or(NEW_ID2_SUFFIX("srst"), sig_srst, tmp, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_srst = cell->module->Or(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->Or(NEW_ID2_SUFFIX("srst"), sig_srst, sig_ce, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
}
} else {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->AndGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->AndGate(NEW_ID2_SUFFIX("srst"), sig_srst, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_srst = cell->module->AndnotGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->AndnotGate(NEW_ID2_SUFFIX("srst"), sig_srst, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
if (pol_ce) {
sig_srst = cell->module->OrnotGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->OrnotGate(NEW_ID2_SUFFIX("srst"), sig_srst, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
sig_srst = cell->module->OrGate(NEW_ID, sig_srst, sig_ce);
sig_srst = cell->module->OrGate(NEW_ID2_SUFFIX("srst"), sig_srst, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
}
}
Expand All @@ -505,14 +501,14 @@ void FfData::unmap_ce() {

if (!is_fine) {
if (pol_ce)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, sig_ce);
sig_d = module->Mux(NEW_ID2_SUFFIX("d"), sig_q, sig_d, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
sig_d = module->Mux(NEW_ID, sig_d, sig_q, sig_ce);
sig_d = module->Mux(NEW_ID2_SUFFIX("d"), sig_d, sig_q, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
if (pol_ce)
sig_d = module->MuxGate(NEW_ID, sig_q, sig_d, sig_ce);
sig_d = module->MuxGate(NEW_ID2_SUFFIX("d"), sig_q, sig_d, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
sig_d = module->MuxGate(NEW_ID, sig_d, sig_q, sig_ce);
sig_d = module->MuxGate(NEW_ID2_SUFFIX("d"), sig_d, sig_q, sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
has_ce = false;
}
Expand All @@ -525,14 +521,14 @@ void FfData::unmap_srst() {

if (!is_fine) {
if (pol_srst)
sig_d = module->Mux(NEW_ID, sig_d, val_srst, sig_srst);
sig_d = module->Mux(NEW_ID2_SUFFIX("d"), sig_d, val_srst, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
sig_d = module->Mux(NEW_ID, val_srst, sig_d, sig_srst);
sig_d = module->Mux(NEW_ID2_SUFFIX("d"), val_srst, sig_d, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
if (pol_srst)
sig_d = module->MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst);
sig_d = module->MuxGate(NEW_ID2_SUFFIX("d"), sig_d, val_srst[0], sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
sig_d = module->MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst);
sig_d = module->MuxGate(NEW_ID2_SUFFIX("d"), val_srst[0], sig_d, sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
has_srst = false;
}
Expand Down Expand Up @@ -705,7 +701,7 @@ void FfData::flip_bits(const pool<int> &bits) {

flip_rst_bits(bits);

Wire *new_q = module->addWire(NEW_ID, width);
Wire *new_q = module->addWire(NEW_ID2_SUFFIX("new_q"), width); // SILIMATE: Improve the naming

if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
Expand All @@ -717,15 +713,15 @@ void FfData::flip_bits(const pool<int> &bits) {
SigSpec new_sig_clr;
if (pol_set) {
if (pol_clr) {
new_sig_clr = module->AndnotGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->AndnotGate(NEW_ID2_SUFFIX("new_clr"), sig_set, sig_clr, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
new_sig_clr = module->AndGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->AndGate(NEW_ID2_SUFFIX("new_clr"), sig_set, sig_clr, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
if (pol_clr) {
new_sig_clr = module->OrGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->OrGate(NEW_ID2_SUFFIX("new_clr"), sig_set, sig_clr, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
new_sig_clr = module->OrnotGate(NEW_ID, sig_set, sig_clr);
new_sig_clr = module->OrnotGate(NEW_ID2_SUFFIX("new_clr"), sig_set, sig_clr, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
}
pol_set = pol_clr;
Expand All @@ -734,28 +730,28 @@ void FfData::flip_bits(const pool<int> &bits) {
sig_clr = new_sig_clr;
}
if (has_clk || has_gclk)
sig_d = module->NotGate(NEW_ID, sig_d);
sig_d = module->NotGate(NEW_ID2_SUFFIX("d"), sig_d, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (has_aload)
sig_ad = module->NotGate(NEW_ID, sig_ad);
module->addNotGate(NEW_ID, new_q, sig_q);
sig_ad = module->NotGate(NEW_ID2_SUFFIX("ad"), sig_ad, cell->get_src_attribute()); // SILIMATE: Improve the naming
module->addNotGate(NEW_ID2_SUFFIX("not"), new_q, sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
else
{
if (has_sr) {
SigSpec not_clr;
if (!pol_clr) {
not_clr = sig_clr;
sig_clr = module->Not(NEW_ID, sig_clr);
sig_clr = module->Not(NEW_ID2_SUFFIX("clr"), sig_clr, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
pol_clr = true;
} else {
not_clr = module->Not(NEW_ID, sig_clr);
not_clr = module->Not(NEW_ID2_SUFFIX("not_clr"), sig_clr, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
if (!pol_set) {
sig_set = module->Not(NEW_ID, sig_set);
sig_set = module->Not(NEW_ID2_SUFFIX("set"), sig_set, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
pol_set = true;
}

SigSpec masked_set = module->And(NEW_ID, sig_set, not_clr);
SigSpec masked_set = module->And(NEW_ID2_SUFFIX("masked_set"), sig_set, not_clr, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
for (auto bit: bits) {
sig_set[bit] = sig_clr[bit];
sig_clr[bit] = masked_set[bit];
Expand All @@ -767,10 +763,10 @@ void FfData::flip_bits(const pool<int> &bits) {
mask.bits()[bit] = State::S1;

if (has_clk || has_gclk)
sig_d = module->Xor(NEW_ID, sig_d, mask);
sig_d = module->Xor(NEW_ID2_SUFFIX("d"), sig_d, mask, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (has_aload)
sig_ad = module->Xor(NEW_ID, sig_ad, mask);
module->addXor(NEW_ID, new_q, mask, sig_q);
sig_ad = module->Xor(NEW_ID2_SUFFIX("ad"), sig_ad, mask, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
module->addXor(NEW_ID2_SUFFIX("xor"), new_q, mask, sig_q, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}

sig_q = new_q;
Expand Down

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