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import chisel3._ | ||
import chisel3.util._ | ||
import chisel3.experimental._ | ||
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||
/** | ||
* == CW_reg_s_pl == | ||
* | ||
* === Abstract === | ||
* | ||
* Register with Synchronous Reset and Load Enable | ||
* | ||
* === Parameters === | ||
* | ||
* | Parameter | Legal Range | Default | Description | | ||
* |--------------|----------------|--------------|------------------------------------------| | ||
* | width | >=1 | 8 | Width of d and q | | ||
* | reset_value | If width <= 31, the value of reset_value must be between 0 and 2<sup>width</sup>-1. If width >= 32, the value of reset_value must be 0. | 0 | Reset value | | ||
* | ||
* === Ports === | ||
* | ||
* | Name | Width | Direction | Description | | ||
* |--------------|----------------|--------------|---------------------------------| | ||
* | d | width | Input | Input data bus | | ||
* | clk | 1 | Input | Clock input | | ||
* | reset_N | 1 | Input | Synchronous reset, active low | | ||
* | enable | 1 | Input | Synchronous enable, active high | | ||
* | q | width | Output | Output data bus | | ||
* | ||
* @param width Width of d and q | ||
* @param reset_value Reset value | ||
*/ | ||
class CW_reg_s_pl(val width: Int, val reset_value: Int) | ||
extends BlackBox( | ||
Map( | ||
"width" -> width, | ||
"reset_value" -> reset_value | ||
) | ||
) | ||
with HasBlackBoxPath { | ||
|
||
// Validate parameters | ||
require(width >= 1, "width must be >= 1") | ||
if (width <= 31) { | ||
require(reset_value >= 0 && reset_value < (1 << width), s"reset_value should be in range [0, ${1 << width})") | ||
} else { | ||
require(reset_value == 0, "reset_value should be == 0") | ||
} | ||
|
||
// Define ports with type annotations | ||
val io = IO(new Bundle { | ||
val d: UInt = Input(UInt(width.W)) | ||
val clk: Clock = Input(Clock()) | ||
val reset_N: Bool = Input(Bool()) | ||
val enable: Bool = Input(Bool()) | ||
val q: UInt = Output(UInt(width.W)) | ||
}) | ||
} |
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import chisel3._ | ||
import chisel3.util._ | ||
import chisel3.experimental._ | ||
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||
/** | ||
* == CW_reset_sync == | ||
* | ||
* === Abstract === | ||
* | ||
* Co-ordinated clearing mechanism between 2 asynchronous clock domains. | ||
* | ||
* === Parameters === | ||
* | ||
* | Parameter | Legal Range | Default | Description | | ||
* |----------------|--------------|----------|----------------------------------------| | ||
* | f_sync_type | [0, 4] | 2 | Type of synchronization mechanism | | ||
* | r_sync_type | [0, 4] | 2 | Type of reset synchronization | | ||
* | clk_d_faster | 1 | 1 | Clock domain relationship | | ||
* | reg_in_prog | [0, 1] | 1 | "in progress" output status signals | | ||
* | tst_mode | [0, 1] | 1 | Scan test mode select input | | ||
* | verif_en | 0 | 0 | Random sampling error insertion | | ||
* | ||
* === Ports === | ||
* | ||
* | Name | Width | Direction | Description | | ||
* |---------------|--------|------------|----------------------------------------| | ||
* | clk_s | 1 bit | input | source domain clock source | | ||
* | rst_s_n | 1 bit | input | source domain asynchronous reset (low) | | ||
* | init_s_n | 1 bit | input | source domain synchronous reset (low) | | ||
* | clr_s | 1 bit | input | source domain clear | | ||
* | clk_d | 1 bit | input | destination domain clock source | | ||
* | rst_d_n | 1 bit | input | destination domain asynchronous reset | | ||
* | init_d_n | 1 bit | input | destination domain synchronous reset | | ||
* | clr_d | 1 bit | input | destination domain clear | | ||
* | test | 1 bit | input | scan test mode select input | | ||
* | clr_sync_s | 1 bit | output | source domain clear for sequential logic | | ||
* | clr_in_prog_s | 1 bit | output | source domain clear sequence in progress | | ||
* | clr_cmplt_s | 1 bit | output | source domain clear sequence complete | | ||
* | clr_in_prog_d | 1 bit | output | destination domain clear sequence in progress | | ||
* | clr_sync_d | 1 bit | output | destination domain clear for sequential logic | | ||
* | clr_cmplt_d | 1 bit | output | destination domain clear sequence complete | | ||
* | ||
* @param f_sync_type Type of synchronization mechanism | ||
* @param r_sync_type Type of reset synchronization | ||
* @param clk_d_faster Clock domain relationship | ||
* @param reg_in_prog "in progress" output status signals | ||
* @param tst_mode Scan test mode select input | ||
* @param verif_en Random sampling error insertion | ||
*/ | ||
class CW_reset_sync( | ||
val f_sync_type: Int = 2, | ||
val r_sync_type: Int = 2, | ||
val clk_d_faster: Int = 1, | ||
val reg_in_prog: Int = 1, | ||
val tst_mode: Int = 1, | ||
val verif_en: Int = 0) | ||
extends BlackBox( | ||
Map( | ||
"f_sync_type" -> f_sync_type, | ||
"r_sync_type" -> r_sync_type, | ||
"clk_d_faster" -> clk_d_faster, | ||
"reg_in_prog" -> reg_in_prog, | ||
"tst_mode" -> tst_mode, | ||
"verif_en" -> verif_en | ||
) | ||
) | ||
with HasBlackBoxPath { | ||
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||
// Validation of all parameters | ||
require(f_sync_type >= 0 && f_sync_type <= 4, s"f_sync_type must be in range [0, 4]") | ||
require(r_sync_type >= 0 && r_sync_type <= 4, s"r_sync_type must be in range [0, 4]") | ||
require(clk_d_faster == 1, "clk_d_faster must be 1") | ||
require(reg_in_prog >= 0 && reg_in_prog <= 1, s"reg_in_prog must be in range [0, 1]") | ||
require(tst_mode >= 0 && tst_mode <= 1, s"tst_mode must be in range [0, 1]") | ||
require(verif_en == 0, "verif_en must be 0") | ||
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||
// Define ports with type annotations | ||
val io = IO(new Bundle { | ||
val clk_s: Clock = Input(Clock()) // source domain clock source | ||
val rst_s_n: Bool = Input(Bool()) // source domain asynchronous reset (low) | ||
val init_s_n: Bool = Input(Bool()) // source domain synchronous reset (low) | ||
val clr_s: Bool = Input(Bool()) // source domain clear | ||
val clk_d: Clock = Input(Clock()) // destination domain clock source | ||
val rst_d_n: Bool = Input(Bool()) // destination domain asynchronous reset | ||
val init_d_n: Bool = Input(Bool()) // destination domain synchronous reset | ||
val clr_d: Bool = Input(Bool()) // destination domain clear | ||
val test: Bool = Input(Bool()) // scan test mode select input | ||
val clr_sync_s: Bool = Output(Bool()) // source domain clear for sequential logic | ||
val clr_in_prog_s: Bool = Output(Bool()) // source domain clear sequence in progress | ||
val clr_cmplt_s: Bool = Output(Bool()) // source domain clear sequence complete | ||
val clr_in_prog_d: Bool = Output(Bool()) // destination domain clear sequence in progress | ||
val clr_sync_d: Bool = Output(Bool()) // destination domain clear for sequential logic | ||
val clr_cmplt_d: Bool = Output(Bool()) // destination domain clear sequence complete | ||
}) | ||
} |
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import chisel3._ | ||
import chisel3.util._ | ||
import chisel3.experimental._ | ||
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/** | ||
* == CW_rotatel == | ||
* | ||
* === Abstract === | ||
* | ||
* Rotate Left | ||
* | ||
* === Parameters === | ||
* | ||
* | Parameter | Legal Range | Default | Description | | ||
* |--------------|--------------|----------|---------------------------------------| | ||
* | wA | >= 2 | 2 | A input width and Z output width | | ||
* | wSH | >= 1 | 1 | SH input width | | ||
* | ||
* === Ports === | ||
* | ||
* | Name | Width | Direction| Description | | ||
* |--------------|--------------|----------|---------------------------------------| | ||
* | A | wA | Input | Input data | | ||
* | SH | wSH | Input | Number of positions to rotate | | ||
* | Z | wA | Output | Rotated output data | | ||
* | ||
* @param wA A input width and Z output width | ||
* @param wSH SH input width | ||
*/ | ||
class CW_rotatel(val wA: Int, val wSH: Int) | ||
extends BlackBox( | ||
Map( | ||
"wA" -> wA, | ||
"wSH" -> wSH | ||
) | ||
) | ||
with HasBlackBoxPath { | ||
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// Validate parameters | ||
require(wA >= 2, s"wA must be >= 2") | ||
require(wSH >= 1, s"wSH must be >= 1") | ||
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// Define ports with type annotations | ||
val io = IO(new Bundle { | ||
val A: UInt = Input(UInt(wA.W)) | ||
val SH: UInt = Input(UInt(wSH.W)) | ||
val Z: UInt = Output(UInt(wA.W)) | ||
}) | ||
} |
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@@ -0,0 +1,49 @@ | ||
import chisel3._ | ||
import chisel3.util._ | ||
import chisel3.experimental._ | ||
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||
/** | ||
* == CW_rotater == | ||
* | ||
* === Abstract === | ||
* | ||
* Rotate Right | ||
* | ||
* === Parameters === | ||
* | ||
* | Parameter | Legal Range | Default | Description | | ||
* |--------------|--------------|----------|--------------------------------------| | ||
* | wA | >= 2 | 2 | A input width and Z output width| | ||
* | wSH | >= 1 | 1 | SH input width | | ||
* | ||
* === Ports === | ||
* | ||
* | Name | Width | Direction| Description | | ||
* |--------------|--------------|----------|--------------------------------------| | ||
* | A | wA | Input | Input data | | ||
* | SH | wSH | Input | Number of positions to rotate | | ||
* | Z | wA | Output | Rotated output data | | ||
* | ||
* @param wA A input width and Z output width | ||
* @param wSH SH input width | ||
*/ | ||
class CW_rotater(val wA: Int, val wSH: Int) | ||
extends BlackBox( | ||
Map( | ||
"wA" -> wA, | ||
"wSH" -> wSH | ||
) | ||
) | ||
with HasBlackBoxPath { | ||
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// Validate parameters | ||
require(wA >= 2, s"wA must be >= 2") | ||
require(wSH >= 1, s"wSH must be >= 1") | ||
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// Define ports with type annotations | ||
val io = IO(new Bundle { | ||
val A: UInt = Input(UInt(wA.W)) | ||
val SH: UInt = Input(UInt(wSH.W)) | ||
val Z: UInt = Output(UInt(wA.W)) | ||
}) | ||
} |
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import chisel3._ | ||
import circt.stage._ | ||
import utest._ | ||
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class reg_s_pl(val width: Int, val reset_value: Int) extends RawModule { | ||
val io = IO(new Bundle { | ||
val d: UInt = Input(UInt(width.W)) | ||
val clk: Clock = Input(Clock()) | ||
val reset_N: Bool = Input(Bool()) | ||
val enable: Bool = Input(Bool()) | ||
val q: UInt = Output(UInt(width.W)) | ||
}) | ||
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// Instantiate the BlackBox | ||
protected val U1: CW_reg_s_pl = Module(new CW_reg_s_pl(width, reset_value)) | ||
U1.io.d := io.d | ||
U1.io.clk := io.clk | ||
U1.io.reset_N := io.reset_N | ||
U1.io.enable := io.enable | ||
io.q := U1.io.q | ||
} | ||
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// Define the TestSuite | ||
object reg_s_pl extends TestSuite { | ||
val tests: Tests = Tests { | ||
test("should instantiate reg_s_pl") { | ||
def top = new reg_s_pl(8, 0) | ||
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val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) | ||
(new ChiselStage).execute( | ||
args = Array("--target-dir", "./build"), | ||
annotations = generator :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog) | ||
) | ||
} | ||
} | ||
} |
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import chisel3._ | ||
import circt.stage._ | ||
import utest._ | ||
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class reset_sync( | ||
val f_sync_type: Int = 2, | ||
val r_sync_type: Int = 2, | ||
val clk_d_faster: Int = 1, | ||
val reg_in_prog: Int = 1, | ||
val tst_mode: Int = 1, | ||
val verif_en: Int = 0) | ||
extends RawModule { | ||
val io = IO(new Bundle { | ||
val clk_s: Clock = Input(Clock()) // source domain clock source | ||
val rst_s_n: Bool = Input(Bool()) // source domain asynchronous reset (low) | ||
val init_s_n: Bool = Input(Bool()) // source domain synchronous reset (low) | ||
val clr_s: Bool = Input(Bool()) // source domain clear | ||
val clk_d: Clock = Input(Clock()) // destination domain clock source | ||
val rst_d_n: Bool = Input(Bool()) // destination domain asynchronous reset | ||
val init_d_n: Bool = Input(Bool()) // destination domain synchronous reset | ||
val clr_d: Bool = Input(Bool()) // destination domain clear | ||
val test: Bool = Input(Bool()) // scan test mode select input | ||
val clr_sync_s: Bool = Output(Bool()) // source domain clear for sequential logic | ||
val clr_in_prog_s: Bool = Output(Bool()) // source domain clear sequence in progress | ||
val clr_cmplt_s: Bool = Output(Bool()) // source domain clear sequence complete | ||
val clr_in_prog_d: Bool = Output(Bool()) // destination domain clear sequence in progress | ||
val clr_sync_d: Bool = Output(Bool()) // destination domain clear for sequential logic | ||
val clr_cmplt_d: Bool = Output(Bool()) // destination domain clear sequence complete | ||
}) | ||
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protected val U1: CW_reset_sync = Module( | ||
new CW_reset_sync( | ||
f_sync_type, | ||
r_sync_type, | ||
clk_d_faster, | ||
reg_in_prog, | ||
tst_mode, | ||
verif_en | ||
) | ||
) | ||
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U1.io.clk_s := io.clk_s | ||
U1.io.rst_s_n := io.rst_s_n | ||
U1.io.init_s_n := io.init_s_n | ||
U1.io.clr_s := io.clr_s | ||
U1.io.clk_d := io.clk_d | ||
U1.io.rst_d_n := io.rst_d_n | ||
U1.io.init_d_n := io.init_d_n | ||
U1.io.clr_d := io.clr_d | ||
U1.io.test := io.test | ||
io.clr_sync_s := U1.io.clr_sync_s | ||
io.clr_in_prog_s := U1.io.clr_in_prog_s | ||
io.clr_cmplt_s := U1.io.clr_cmplt_s | ||
io.clr_in_prog_d := U1.io.clr_in_prog_d | ||
io.clr_sync_d := U1.io.clr_sync_d | ||
io.clr_cmplt_d := U1.io.clr_cmplt_d | ||
} | ||
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object reset_sync extends TestSuite { | ||
val tests: Tests = Tests { | ||
test("should instantiate reset_sync") { | ||
def top = new reset_sync( | ||
f_sync_type = 2, | ||
r_sync_type = 2, | ||
clk_d_faster = 1, | ||
reg_in_prog = 1, | ||
tst_mode = 1, | ||
verif_en = 0 | ||
) | ||
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val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) | ||
(new ChiselStage).execute( | ||
args = Array("--target-dir", "./build"), | ||
annotations = generator :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog) | ||
) | ||
} | ||
} | ||
} |
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