feat: convert CW_lz*

Closes #25

chipware/src/CW_lza.scala

@@ -0,0 +1,44 @@
+import chisel3._
+import chisel3.experimental._
+import chisel3.util._
+
+/**
+  * == CW_lza ==
+  *
+  * === Abstract ===
+  *
+  * Leading Zeros Anticipator.
+  * CW_lza will predict the number of leading zeros in between unsigned inputs a and b which are respectively the minuend and subtrahend terms in a difference.
+  *
+  * === Parameters ===
+  *
+  * | Parameter       | Legal Range | Default | Description          |
+  * |-----------------|-------------|---------|----------------------|
+  * | width           | 2 to 28 | 4       | Width of input arguments a and b |
+  *
+  * === Ports ===
+  *
+  * | Name   | Width         | Direction | Description |
+  * |--------|---------------|-----------|-------------|
+  * | a      | width         | Input     | Unsigned Minuend |
+  * | b      | width         | Input     | Unsigned Subtrahend |
+  * | count  | BWBOinputWidth| Output    | Anticipated number of leading zeros |
+  *
+  * @param width          Width of input arguments a and b
+  */
+class CW_lza(val width: Int = 4)
+    extends BlackBox(
+      Map(
+        "width" -> width
+      )
+    )
+    with HasBlackBoxPath {
+  require(width >= 2 && width <= 28, "width must be in 2 to 28")
+  protected val BWBOinputWidth: Int = log2Ceil(width)
+
+  val io = IO(new Bundle {
+    val a:     UInt = Input(UInt(width.W))
+    val b:     UInt = Input(UInt(width.W))
+    val count: UInt = Output(UInt(BWBOinputWidth.W))
+  })
+}

chipware/src/CW_lzcount.scala

@@ -0,0 +1,50 @@
+import chisel3._
+import chisel3.experimental._
+import chisel3.util._
+
+/**
+  * == CW_lzcount ==
+  *
+  * === Abstract ===
+  *
+  * Leading Zero Counter.
+  * Determines the number of leading 0’s in the A input signal.
+  * The result is provided as a binary number on the Z output.
+  *
+  * === Parameters ===
+  *
+  * | Parameter  | Legal Range  | Default  | Description  |
+  * |---------------|--------------|--------------|----------------|
+  * | wA  | wA >= 2  | 2  | A input width  |
+  * | wZ  | wZ >= 1  | 1  | Z output width  |
+  *
+  * === Ports ===
+  *
+  * | Name  | Width  | Direction | Description  |
+  * |--------|------------|-----------|------------------------|
+  * | A  | wA  | Input  | Input data |
+  * | Z  | wZ  | Output  | Number of leading zeroes in A |
+  * | All0  | 1  | Output  | Indication that A=0 |
+  *
+  * @param wA  A input width
+  * @param wZ  Z output width
+  */
+class CW_lzcount(val wA: Int = 2, val wZ: Int = 1)
+    extends BlackBox(
+      Map(
+        "wA" -> wA,
+        "wZ" -> wZ
+      )
+    )
+    with HasBlackBoxPath {
+  // Validation of all parameters
+  require(wA >= 2, "wA must be >= 2")
+  require(wZ >= 1, "wZ must be >= 1")
+
+  // Define ports with type annotations
+  val io = IO(new Bundle {
+    val A:    UInt = Input(UInt(wA.W))
+    val Z:    UInt = Output(UInt(wZ.W))
+    val All0: Bool = Output(Bool())
+  })
+}

chipware/src/CW_lzd.scala

@@ -0,0 +1,45 @@
+import chisel3._
+import chisel3.experimental._
+import chisel3.util._
+
+/**
+  * == CW_lzd ==
+  *
+  * === Abstract ===
+  *
+  * Leading Zeroes Detector.
+  * Computes the count of leading zeros in the input argument and outputs this count as an unsigned binary number.
+  *
+  * === Parameters ===
+  *
+  * | Parameter    | Legal Range  | Default  | Description  |
+  * |--------------|--------------|----------|--------------|
+  * | a_width      | a_width >= 1 | 8        | Input string width |
+  *
+  * === Ports ===
+  *
+  * | Name  | Width         | Direction | Description  |
+  * |-------|---------------|-----------|--------------|
+  * | a     | a_width       | Input     | Input port |
+  * | enc   | ceil(log2[a_width]+1) | Output    | Number of leading zeroes in a before the first one. |
+  * | dec   | a_width       | Output    | One hot decode of a |
+  *
+  * @param a_width  Input string width
+  */
+class CW_lzd(val a_width: Int = 8)
+    extends BlackBox(
+      Map(
+        "a_width" -> a_width
+      )
+    )
+    with HasBlackBoxPath {
+  // Validation of all parameters
+  require(a_width >= 1, "a_width must be >= 1")
+  protected val log_a_width: Int = log2Ceil(a_width)
+  // Define ports with type annotations
+  val io = IO(new Bundle {
+    val a:   UInt = Input(UInt(a_width.W))
+    val enc: UInt = Output(UInt((log_a_width + 1).W))
+    val dec: UInt = Output(UInt(a_width.W))
+  })
+}

chipware/test/src/utest/lza.scala

@@ -0,0 +1,33 @@
+import chisel3._
+import circt.stage._
+import chisel3.util._
+import utest._
+
+class lza(val width: Int = 4) extends RawModule {
+  protected val BWBOinputWidth: Int = log2Ceil(width)
+
+  val io = IO(new Bundle {
+    val a:     UInt = Input(UInt(width.W))
+    val b:     UInt = Input(UInt(width.W))
+    val count: UInt = Output(UInt(BWBOinputWidth.W))
+  })
+
+  protected val U1: CW_lza = Module(new CW_lza(width))
+  U1.io.a  := io.a
+  U1.io.b  := io.b
+  io.count := U1.io.count
+}
+
+object lza extends TestSuite {
+  val tests: Tests = Tests {
+    test("should instantiate lza") {
+      def top = new lza(4)
+
+      val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
+      (new ChiselStage).execute(
+        args        = Array("--target-dir", "./build"),
+        annotations = generator :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)
+      )
+    }
+  }
+}

chipware/test/src/utest/lzcount.scala

@@ -0,0 +1,30 @@
+import chisel3._
+import circt.stage._
+import utest._
+
+class lzcount(val wA: Int = 2, val wZ: Int = 1) extends RawModule {
+  val io = IO(new Bundle {
+    val A:    UInt = Input(UInt(wA.W))
+    val Z:    UInt = Output(UInt(wZ.W))
+    val All0: Bool = Output(Bool())
+  })
+
+  protected val U1: CW_lzcount = Module(new CW_lzcount(wA, wZ))
+  U1.io.A := io.A
+  io.Z    := U1.io.Z
+  io.All0 := U1.io.All0
+}
+
+object lzcount extends TestSuite {
+  val tests: Tests = Tests {
+    test("should instantiate lzcount") {
+      def top = new lzcount(2, 1)
+
+      val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
+      (new ChiselStage).execute(
+        args        = Array("--target-dir", "./build"),
+        annotations = generator :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)
+      )
+    }
+  }
+}

chipware/test/src/utest/lzd.scala

@@ -0,0 +1,32 @@
+import chisel3._
+import circt.stage._
+import chisel3.util._
+import utest._
+
+class lzd(val a_width: Int = 8) extends RawModule {
+  protected val log_a_width: Int = log2Ceil(a_width)
+  val io = IO(new Bundle {
+    val a:   UInt = Input(UInt(a_width.W))
+    val enc: UInt = Output(UInt((log_a_width + 1).W))
+    val dec: UInt = Output(UInt(a_width.W))
+  })
+
+  protected val U1: CW_lzd = Module(new CW_lzd(a_width))
+  U1.io.a := io.a
+  io.enc  := U1.io.enc
+  io.dec  := U1.io.dec
+}
+
+object lzd extends TestSuite {
+  val tests: Tests = Tests {
+    test("should instantiate lzd") {
+      def top = new lzd(8)
+
+      val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
+      (new ChiselStage).execute(
+        args        = Array("--target-dir", "./build"),
+        annotations = generator :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)
+      )
+    }
+  }
+}