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Add CI scripts and setup files to automate installation #130
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- Added Makefile for build and test orchestration. - Added multiple CI scripts for environment setup and dependency installation: - build_regress_simulator.sh - build_spike_rvls.sh - clone-submodules.sh - install-elfio.sh - install-libsdl.sh - install-openjdk.sh - install-riscv-gnu-toolchain.sh - install-rvls.sh - install-sbt.sh - install-spike-spinalhdl.sh - install-verilator.sh - Added README.md in src/test for installation and test-related documentation.
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ADDCFLAGS += -CFLAGS -lSDL2 |
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Why removing ADDCFLAGS += -CFLAGS -lSDL2 ?
It seems it is the reason why the CI fail ?
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to include this ADDCFLAGS += -LDFLAGS -L$(realpath ${SPIKE_LIB})
For me it works fine without ADDCFLAGS += -CFLAGS -lSDL2
I can put it back if that's the problem.
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I see in the CI logs :
main.cpp:(.text+0x406e): undefined reference to SDL_Init' /usr/bin/ld: main.cpp:(.text+0x4099): undefined reference to
SDL_CreateWindow'
/usr/bin/ld: main.cpp:(.text+0x40aa): undefined reference to SDL_CreateRenderer' /usr/bin/ld: main.cpp:(.text+0x40c4): undefined reference to
SDL_CreateTexture'
Seems it is related ^^
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These modifications aim to eliminate the need for sudo by sourcing libsdl and elfio locally.
Thanks :D |
Hi @Dolu1990 ,
# Switch to the appropriate branch
git checkout rvls-update
# Perform the full installation
make install This command installs the core, toolchain, simulators, and tests in one step.
ccache g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd \
-DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none \
-Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable \
-Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++14 -Iobj_dir \
-INaxRiscv/ext/riscv-isa-sim/riscv -INaxRiscv/ext/riscv-isa-sim/fesvr -INaxRiscv/ext/riscv-isa-sim/softfloat \
-INaxRiscv/ext/riscv-isa-sim/build -INaxRiscv/ext/include -g -rdynamic -O3 -DTRACE -std=gnu++14 \
-c -o VNaxRiscv__Trace__7__Slow.o VNaxRiscv__Trace__7__Slow.cpp
g++ -I. -MMD -I/home/runner/tools/share/verilator/include -I/home/runner/tools/share/verilator/include/vltstd - \
DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool- \
operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-\
variable -Wno-shadow -std=c++14 -Iobj_dir -I/home/runner/work/NaxRiscv/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/\
runner/work/NaxRiscv/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/runner/work/NaxRiscv/NaxRiscv/ext/riscv-isa-sim/\
softfloat -I/home/runner/work/NaxRiscv/NaxRiscv/ext/riscv-isa-sim/build -I -g -rdynamic -O3 -DTRACE -std=gnu++14 \
-c -o VNaxRiscv__Trace__7__Slow.o VNaxRiscv__Trace__7__Slow.cpp
echo "" > VNaxRiscv__ALL.verilator_deplist.tmp
Could you confirm if the |
Hi,
Which configuration ?
There is no specific setup. All comes from this repo. This is vanilla github actions : https://github.com/SpinalHDL/NaxRiscv/blob/main/.github/workflows/scala.yml#L15 |
Hi,
The issue was that the |
Moved the installation paths of ELFIO and SDL libraries from INCLUDE_DIR to SPIKE_DIR for better organization and grouping of related dependencies.
Reason: Removed the local installation of the RISC-V toolchain as it significantly increases installation time. The toolchain will now be assumed to be pre-installed or managed externally.
ci/install-elfio.sh ci/install-libsdl.sh ci/install-spike-spinalhdl.sh Replaced with: NaxRiscv/ci/install-libsdl-elfio-spikespinalhdl.sh Reason: Consolidated the installation of ELFIO, libSDL, and Spike into a single script (install-libsdl-elfio-spikespinalhdl.sh) to streamline the process and reduce redundancy.
Changes: Integrated the installation of ELFIO and SDL into the script to ensure all dependencies are handled during the build process. Reason: Simplifies the setup by automating the installation of required libraries (ELFIO and SDL) before building Spike and RVLS, reducing manual steps and improving reliability.
Changes: Updated SPIKE_INCLUDE and SPIKE_LIB paths to correctly point to /include and /lib respectively. Reason: Ensures the Makefile accurately references the Spike installation's include and library directories(ELFIO & SDL), resolving potential build issues caused by incorrect paths.
Changes: Removed redundant test file definitions and streamlined the install-toolchain process. Integrated the installation of ELFIO and SDL into the install-toolchain target using the consolidated script install-libsdl-elfio-spikespinalhdl.sh. Removed separate installation targets for ELFIO and SDL, as they are now handled by the consolidated script. Added install-core as a prerequisite for install-toolchain-initial to ensure submodules are cloned before toolchain installation. Added a new test-regression target for running NaxRiscv regression tests. Improved cleanup targets (clean-submodules, clean-toolchain, and clean-toolchain-all) for better organization. Reason: Simplifies the build process by consolidating ELFIO and SDL installation into a single script. Ensures proper dependency management by cloning submodules before toolchain installation. Adds regression testing support for better validation of the NaxRiscv implementation. Improves maintainability and clarity of the Makefile.
src/test/README.md: Updated the description of make install-toolchain-initial to reflect the removal of the RISC-V GNU toolchain installation. Clarified the purpose of make install-core to indicate that it clones submodules and applies necessary patches. Enhanced the description of make install to provide a more detailed explanation of the full installation process. Updated the make build-spike-rvls description to specify that it rebuilds Spike (including ELFIO and SDL libraries) and RVLS after modifications. .gitignore: Added toolchain/ to the list of ignored directories to prevent toolchain-related files from being tracked by Git. Reason: Improves documentation clarity by accurately reflecting changes to the build and installation process. Ensures the .gitignore file is up-to-date with the project's directory structure, avoiding unnecessary file tracking.
.github/workflows/scala.yml: Simplified the tool installation process by replacing separate install_cached and install_uncached steps with a single install_all step. Removed the explicit installation of SpinalHDL, as it is now handled by the make install command. .github/workflows/tools.sh: Added a new install_all function that sets the NAXRISCV environment variable and runs make install to handle the complete installation process. Reason: Streamlines the CI workflow by consolidating tool installation into a single step. Ensures consistency by leveraging the make install command, which handles all dependencies and installations (including SpinalHDL, ELFIO, SDL, Spike, and RVLS).
… additional plugin options Description: - Added support for command-line argument parsing using scopt.OParser. - Introduced configuration variables such as withRvc, withFloat, withDouble, withSupervisor, and withUser to enable or disable specific features dynamically. - Extended the Config.plugins method to accept and utilize these new options. - Refactored the Gen and Gen64 objects to handle dynamic configurations, allowing greater flexibility for customizing the generation process. - Improved code readability and maintainability with structured argument parsing and clearer configuration management.
- Added support for new CLI options: withRvc, withFloat, withDouble, workspace-path, workspace-name, and others for enhanced simulation configuration. - Implemented ISA extensions for RV32/64I, MA, F, D, and C support in simulation traces. - Enabled loading and execution of additional binary data formats via load-u32. - Improved handling of ELF file symbols for start, pass, and fail with dynamic PC setting and result logging. - Introduced workspace and output directory management for structured simulation artifacts. - Integrated Linux command handling for getc and putc workflows in buildroot simulations. - Refactored test result recording with detailed logs and success/fail file generation. - Enhanced DualSim and standard simulation execution logic for multi-test scenarios.
…SocDemo - Extended SocDemo to include new parameters: withRvc, withFloat, and withDouble. - Updated TilelinkNaxRiscvFiber configuration to support these options. - Improved flexibility for CPU configuration in simulation.
- Added loadU32 method to TraceBackend for 32-bit data loading. - Enhanced trap method to include fault_addr parameter for detailed fault handling. - Updated DummyBackend, FileBackend, and RvlsBackend implementations to support these changes. - Improved logging in FileBackend to reflect the new trap and loadU32 functionalities.
…simulation - Introduced a trait and a queue for organizing tasks during boot simulation. - Added WaitPutc, DoSuccess, and DoGetc classes for specific task scheduling scenarios. - Improved handling of PUTC with putcTarget and putcHistory to trigger actions based on output. - Enhanced GETC handling to support custom input via customCin queue in addition to system input. - Added utility methods like testScheduleQueueNext and endsWith for managing task execution and string matching. - Ensured compatibility with existing simulation flows while enabling more complex boot sequences.
…t options - Updated getCoherentConfig to include parameters for RVC (withRvc), single-precision floating-point (withFloat), and double-precision floating-point (withDouble). - Ensured that the configuration now supports additional customization for RISC-V features like compressed and floating-point instructions. - Maintained backward compatibility by setting default values for the new parameters.
- Refactored add method to accept an ISA string for more flexible CPU initialization in tracers. - Improved support for multiple register files, including both integer and floating-point register write events. - Added handling for FS bits in MSTATUS when writing to FCSR, setting the status to dirty. - Enhanced trap handling to include fault address (tval and its width) for improved debugging and reporting. - Updated backend interactions to properly handle floating-point writes and FS state changes. - Maintained backward compatibility with the existing structure while extending functionality.
- Introduced fsDirty signal to track when FS bits in MSTATUS are set to dirty. - Added logic to detect writes to CSR registers related to floating-point operations (FRM, FCSR, FFLAGS) and set fsDirty accordingly. - Ensured compatibility by conditionally enabling fsDirty tracking only when RVF is present. - Improved observability of floating-point status changes during CSR write operations.
- Change Spike installation prefix to project-local directory (ext/riscv-isa-sim/) - Add shared library (package.so) compilation step linking Spike components - Include Boost Regex/System and pthread dependencies in shared library - Update build comments to clarify library compilation
- Update Spike installation prefix to use SPIKE_NAX_HOME instead of global RISCV path - Add shared library (package.so) compilation step after main build
- Reorganize documentation hierarchy with clearer section headers - Add detailed RVLS regression testing methodology with: * Step-by-step configuration examples * Artifact directory structure documentation * Supported ISA configuration matrix - Expand feature flag matrix with test coverage details - Include complete test generation parameters reference - Remove redundant horizontal separators for better readability - Update installation section with explicit path reference - Add test automation workflow description for both methods: * RVLS-based verification process * Traditional regression testing approach - Clarify advanced configuration options with parameter tables
- Check if VERILATOR_ROOT is defined to use custom installs verilator binary - Fallback to system-wide verilator if VERILATOR_ROOT is not set - Resolves verilator_bin not found error by ensuring correct /bin subdirectory
- Added set -e to stop the script on errors - Refactored variable names for better clarity - Fixed the order of git clone and git checkout commands - Added explicit installation messages
- Use relative path for VNaxRiscv binary - Remove VERILATOR_ROOT conditional - Update make command to use obj_dir/ directly
- Unset VERILATOR_ROOT before cloning and building Verilator - Removed redundant make install step
…event commit failures when traceIt is disabled. Previously, when traceIt was set to false, the absence of spikeLogCommit() caused commit failures during simulation. This change ensures that spikeLogCommit() is always called, regardless of the traceIt setting, while keeping spikeDebug() optional. Updated SocSim logic: - Always enable spikeLogCommit() to maintain proper commit handling. - Keep spikeDebug() conditional based on traceIt. This prevents missing commits and ensures stable simulation behavior.
…then through RVLS (lockstep)
Weird, i don't know what is happening with the github action :
Did you enabled some sort of user hosted runner ? |
No, I actually added the stage that runs regression tests with RVLS to the pipeline. However, the pipeline crashed due to insufficient memory, caused by the large Spike.log file generated by RVLS. My initial plan was to disable logging and restart the pipeline, but I haven't yet found a way to disable Spike.log without crashing the system. This is the message I received when the pipeline failed. |
…la to avoid GitHub Actions timeout Description: Commented out multiple doTest calls to prevent the job from exceeding the 360-minute execution limit on GitHub Actions. Only the rv64imafdcsu configuration remains active with RVLS simulation. This change aims to reduce execution time and prevent workflow failures due to timeouts.
Hi ^^ We can confirm that the version enabling regression tests through SoCSim and RVLS is fully functional ! In the GitHub workflow pipeline, I first run regression tests via |
Nice :D |
Hi @Dolu1990,
Thanks