Use clog2 helper function to improve clarity. #116

SystemRDL · Dec 20, 2024 · a15178c · a15178c
1 parent 80a46a0
commit a15178c
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/src/peakrdl_regblock/field_logic/generators.py b/src/peakrdl_regblock/field_logic/generators.py
@@ -7,7 +7,7 @@
 
 from ..struct_generator import RDLStructGenerator
 from ..forloop_generator import RDLForLoopGenerator
-from ..utils import get_indexed_path
+from ..utils import get_indexed_path, clog2
 from ..identifier_filter import kw_filter as kwf
 
 if TYPE_CHECKING:
@@ -362,7 +362,7 @@ def assign_external_reg_outputs(self, node: 'RegNode') -> None:
     def assign_external_block_outputs(self, node: 'AddressableNode') -> None:
         prefix = "hwif_out." + get_indexed_path(self.exp.ds.top_node, node)
         strb = self.exp.dereferencer.get_external_block_access_strobe(node)
-        addr_width = (node.size - 1).bit_length()
+        addr_width = clog2(node.size)
 
         retime = False
         if isinstance(node, RegfileNode):

diff --git a/src/peakrdl_regblock/hwif/generators.py b/src/peakrdl_regblock/hwif/generators.py
@@ -6,6 +6,7 @@
 from ..struct_generator import RDLFlatStructGenerator
 from ..identifier_filter import kw_filter as kwf
 from ..sv_int import SVInt
+from ..utils import clog2
 
 if TYPE_CHECKING:
     from systemrdl.node import Node, SignalNode, AddressableNode, RegfileNode
@@ -194,7 +195,7 @@ def get_typdef_name(self, node:'Node', suffix: str = "") -> str:
 
     def _add_external_block_members(self, node: 'AddressableNode') -> None:
         self.add_member("req")
-        self.add_member("addr", (node.size - 1).bit_length())
+        self.add_member("addr", clog2(node.size))
         self.add_member("req_is_wr")
         self.add_member("wr_data", self.hwif.ds.cpuif_data_width)
         self.add_member("wr_biten", self.hwif.ds.cpuif_data_width)