Update descriptions on 64 bit instructions

src/rars/riscv/instructions/ADDIW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class ADDIW extends ImmediateInstruction {
     public ADDIW() {
-        super("addiw t1,t2,-100", "Addition immediate: set t1 to (t2 plus signed 12-bit immediate)", "000",true);
+        super("addiw t1,t2,-100", "Addition immediate: set t1 to (t2 plus signed 12-bit immediate) using only the lower 32 bits", "000",true);
     }
 
     public long compute(long value, long immediate) {

src/rars/riscv/instructions/ADDW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class ADDW extends ArithmeticW {
     public ADDW() {
-        super("addw t1,t2,t3", "Addition: set t1 to (t2 plus t3)",
+        super("addw t1,t2,t3", "Addition: set t1 to (t2 plus t3) using only the lower 32 bits",
                 "0000000", "000",new ADD());
     }
 }

src/rars/riscv/instructions/AUIPC.java

@@ -40,7 +40,6 @@ public AUIPC() {
 
     public void simulate(ProgramStatement statement) {
         int[] operands = statement.getOperands();
-        // TODO: make sure this is fine
         RegisterFile.updateRegister(operands[0], RegisterFile.getProgramCounter() - INSTRUCTION_LENGTH + (operands[1] << 12));
     }
 }

src/rars/riscv/instructions/DIVUW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class DIVUW extends ArithmeticW {
     public DIVUW() {
-        super("divuw t1,t2,t3", "Multiplication: set t1 to the lower 32 bits of t2*t3",
+        super("divuw t1,t2,t3", "Division: set t1 to the result of t2/t3 using unsigned division limited to 32 bits",
                 "0000001", "101",new DIVU());
     }
 

src/rars/riscv/instructions/DIVW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class DIVW extends ArithmeticW {
     public DIVW() {
-        super("divw t1,t2,t3", "Multiplication: set t1 to the lower 32 bits of t2*t3",
+        super("divw t1,t2,t3", "Division: set t1 to the result of t2/t3 using only the lower 32 bits",
                 "0000001", "100",new DIV());
     }
 }

src/rars/riscv/instructions/LD.java

@@ -3,10 +3,9 @@
 import rars.Globals;
 import rars.riscv.hardware.AddressErrorException;
 
-// todo: update description
 public class LD extends Load {
     public LD() {
-        super("ld t1, -100(t2)", "Set t1 to contents of effective memory word address", "011",true);
+        super("ld t1, -100(t2)", "Set t1 to contents of effective memory double word address", "011",true);
     }
 
     public long load(int address) throws AddressErrorException {

src/rars/riscv/instructions/LWU.java

@@ -3,10 +3,9 @@
 import rars.Globals;
 import rars.riscv.hardware.AddressErrorException;
 
-// todo: update description
 public class LWU extends Load {
     public LWU() {
-        super("lwu t1, -100(t2)", "Set t1 to contents of effective memory word address", "110",true);
+        super("lwu t1, -100(t2)", "Set t1 to contents of effective memory word address without sign-extension", "110",true);
     }
 
     public long load(int address) throws AddressErrorException {

src/rars/riscv/instructions/MULW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class MULW extends ArithmeticW {
     public MULW() {
-        super("mulw t1,t2,t3", "Multiplication: set t1 to the lower 32 bits of t2*t3",
+        super("mulw t1,t2,t3", "Multiplication: set t1 to the lower 32 bits of t2*t3 using only the lower 32 bits of the input",
                 "0000001", "000",new MUL());
     }
 }

src/rars/riscv/instructions/REMUW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class REMUW extends ArithmeticW {
     public REMUW() {
-        super("remuw t1,t2,t3", "Multiplication: set t1 to the lower 32 bits of t2*t3",
+        super("remuw t1,t2,t3", "Remainder: set t1 to the remainder of t2/t3 using unsigned division limited to 32 bits",
                 "0000001", "111",new REMU());
     }
 }

src/rars/riscv/instructions/REMW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class REMW extends ArithmeticW {
     public REMW() {
-        super("remw t1,t2,t3", "Multiplication: set t1 to the lower 32 bits of t2*t3",
+        super("remw t1,t2,t3", "Remainder: set t1 to the remainder of t2/t3 using only the lower 32 bits",
                 "0000001", "110",new REM());
     }
 }

src/rars/riscv/instructions/SD.java

@@ -3,10 +3,9 @@
 import rars.Globals;
 import rars.riscv.hardware.AddressErrorException;
 
-// todo: update description
 public class SD extends Store {
     public SD() {
-        super("sd t1, -100(t2)", "Store word : Store contents of t1 into effective memory word address", "011",true);
+        super("sd t1, -100(t2)", "Store double word : Store contents of t1 into effective memory double word address", "011",true);
     }
 
     public void store(int address, long data) throws AddressErrorException {

src/rars/riscv/instructions/SLLIW.java

@@ -5,10 +5,9 @@
 import rars.riscv.BasicInstruction;
 import rars.riscv.BasicInstructionFormat;
 
-// TODO: description
 public class SLLIW extends BasicInstruction {
     public SLLIW() {
-        super("slliw t1,t2,10", "Shift left logical : Set t1 to result of shifting t2 left by number of bits specified by immediate",
+        super("slliw t1,t2,10", "Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by immediate",
                 BasicInstructionFormat.R_FORMAT, "0000000 ttttt sssss 001 fffff 0011011",true);
     }
 

src/rars/riscv/instructions/SLLW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class SLLW extends ArithmeticW {
     public SLLW() {
-        super("sllw t1,t2,t3", "Shift left logical: Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3",
+        super("sllw t1,t2,t3", "Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3",
                 "0000000", "001",new SLL());
     }
 }

src/rars/riscv/instructions/SLTIU.java

@@ -35,8 +35,4 @@ public SLTIU() {
     public long compute(long value, long immediate) {
         return (Long.compareUnsigned(value, immediate) < 0) ? 1 : 0;
     }
-    /* TODO make sure this is correct
-    public int compute(int value, int immediate) {
-        return (Integer.compareUnsigned(value, immediate) < 0) ? 1 : 0;
-    }*/
 }

src/rars/riscv/instructions/SLTU.java

@@ -36,9 +36,4 @@ public SLTU() {
     public long compute(long value, long value2) {
         return (Long.compareUnsigned(value, value2) < 0) ? 1 : 0;
     }
-     /* TODO make sure this is correct
-    public int computeW(int value, int value2) {
-        return (Integer.compareUnsigned(value, value2) < 0) ? 1 : 0;
-    }
-      */
 }

src/rars/riscv/instructions/SRAIW.java

@@ -6,10 +6,9 @@
 import rars.riscv.BasicInstruction;
 import rars.riscv.BasicInstructionFormat;
 
-// TODO: description
 public class SRAIW extends BasicInstruction {
     public SRAIW() {
-        super("sraiw t1,t2,10", "Shift right arithmetic : Set t1 to result of sign-extended shifting t2 right by number of bits specified by immediate",
+        super("sraiw t1,t2,10", "Shift right arithmetic (32 bit): Set t1 to result of sign-extended shifting t2 right by number of bits specified by immediate",
                 BasicInstructionFormat.R_FORMAT, "0100000 ttttt sssss 101 fffff 0011011",true);
     }
 

src/rars/riscv/instructions/SRAW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class SRAW extends ArithmeticW {
     public SRAW() {
-        super("sraw t1,t2,t3", "Shift left logical: Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3",
+        super("sraw t1,t2,t3", "Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3",
                 "0100000", "101",new SRA());
     }
 }

src/rars/riscv/instructions/SRLIW.java

@@ -7,7 +7,7 @@
 
 public class SRLIW extends BasicInstruction {
     public SRLIW() {
-        super("srliw t1,t2,10", "Shift right logical : Set t1 to result of shifting t2 right by number of bits specified by immediate",
+        super("srliw t1,t2,10", "Shift right logical (32 bit): Set t1 to result of shifting t2 right by number of bits specified by immediate",
                 BasicInstructionFormat.R_FORMAT, "0000000 ttttt sssss 101 fffff 0011011",true);
     }
 

src/rars/riscv/instructions/SRLW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class SRLW extends ArithmeticW {
     public SRLW() {
-        super("srlw t1,t2,t3", "Shift left logical: Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3",
+        super("srlw t1,t2,t3", "Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3",
                 "0000000", "101",new SRL());
     }
 }

src/rars/riscv/instructions/SUBW.java

@@ -1,9 +1,8 @@
 package rars.riscv.instructions;
 
-// TODO: update description
 public class SUBW extends ArithmeticW {
     public SUBW() {
-        super("subw t1,t2,t3", "Addition: set t1 to (t2 plus t3)",
+        super("subw t1,t2,t3", "Subtraction: set t1 to (t2 minus t3) using only the lower 32 bits",
                 "0100000", "000",new SUB());
     }
 }