verilog code insert

docs/info.md

@@ -17,4 +17,4 @@ Attach a lowpass filters to the PWM outputs and you get analog audio signal wave
 
 ## External hardware
 
-Lowpass filters for the PWM output.
+Lowpass filters for the PWM outputs.

info.yaml

@@ -8,30 +8,30 @@ project:
   clock_hz:     12000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt06_thorkn_audiochip_v2"
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:        
-    - "project.v"
+    - "PWMaudio.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "freq_bit_in_0"
+  ui[1]: "freq_bit_in_1"
+  ui[2]: "freq_bit_in_2"
+  ui[3]: "freq_bit_in_3"
+  ui[4]: "freq_bit_in_4"
+  ui[5]: "freq_bit_in_5"
+  ui[6]: "freq_bit_in_6"
+  ui[7]: "freq_bit_in_7"
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
+  uo[0]: "pwm_1_out"
+  uo[1]: "pwm_2_out"
   uo[2]: ""
   uo[3]: ""
   uo[4]: ""
@@ -40,14 +40,14 @@ pinout:
   uo[7]: ""
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "adsr_choice_in_0"
+  uio[1]: "adsr_choice_in_1"
+  uio[2]: "adsr_choice_in_2"
+  uio[3]: "adsr_switch_in"
+  uio[4]: "freq_bit_in_8"
+  uio[5]: "freq_bit_in_9"
+  uio[6]: "freq_bit_in_10"
+  uio[7]: "freq_bit_in_11"
 
 # Do not change!
 yaml_version: 6