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Zheng ir interpreter #106

Merged
merged 6 commits into from
Oct 16, 2023
Merged

Zheng ir interpreter #106

merged 6 commits into from
Oct 16, 2023

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hz050504
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hz050504 and others added 6 commits October 10, 2023 07:53
modify:
· moved the Interpret call in RunUtils
· mems type from Array to mutable.Map
· fix block traversal from recursion to while loop
· fix condition for exit interpret
add:
· implement MemoryLoad and MemoryStore
· Initial SP, FP and LR
remove:
· size check for BitVecLiteral in LocalAssign
- Refactor the run part into the Interpret() function
- Moved the input Program from the class to the Interpret() function.
- Added a InterpretTests class.
- Extracted MemoryLoad and MemoryStore functionality to getMemory() and setMemory().
- Changed the initial values for SP, FP, and LR to be more reasonable.
- Modified BitVecLiteral value logging in hexadecimal format.
- Made interpretProcedure(), interpretBlock(), and interpretStatement() private.
- Added a break when nextBlock is determined.
- Added a logLevel variable to control logging information.
# Conflicts:
#	src/main/scala/ir/Interpret.scala
#	src/main/scala/util/RunUtils.scala
@l-kent l-kent merged commit 58bf99e into main Oct 16, 2023
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2 participants