Fixed typos.

VHDL · Apr 16, 2023 · 004fb0e · 004fb0e
1 parent 253507b
commit 004fb0e
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Showing 4 changed files with 8 additions and 8 deletions.
diff --git a/pyVHDLModel/Namespace.py b/pyVHDLModel/Namespace.py
@@ -78,7 +78,7 @@ def FindComponent(self, componentSymbol: ComponentInstantiationSymbol):
 		from pyVHDLModel.DesignUnit import Component
 
 		try:
-			element = self._elements[componentSymbol.NormalizedIdentifier]
+			element = self._elements[componentSymbol.Name.NormalizedIdentifier]
 			if isinstance(element, Component):
 				return element
 			else:

diff --git a/pyVHDLModel/STD.py b/pyVHDLModel/STD.py
@@ -36,7 +36,7 @@
 
 from pyVHDLModel             import Library
 from pyVHDLModel.Name        import SimpleName, SelectedName, AllName
-from pyVHDLModel.Symbol      import LibraryReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol, PackageSymbol
+from pyVHDLModel.Symbol      import LibraryReferenceSymbol, PackageMemberReferenceSymbol, AllPackageMembersReferenceSymbol, PackageSymbol
 from pyVHDLModel.DesignUnit  import LibraryClause, UseClause, Package, PackageBody
 
 
@@ -77,7 +77,7 @@ def _AddPackageClause(self, packages: Iterable[str]):
 			if members.lower() == "all":
 				symbols.append(AllPackageMembersReferenceSymbol(AllName(packageName)))
 			else:
-				symbols.append(PackageMembersReferenceSymbol(SelectedName(members, packageName)))
+				symbols.append(PackageMemberReferenceSymbol(SelectedName(members, packageName)))
 
 		useClause = UseClause(symbols)
 		self._contextItems.append(useClause)

diff --git a/pyVHDLModel/Symbol.py b/pyVHDLModel/Symbol.py
@@ -162,7 +162,7 @@ def Package(self, value: 'Package') -> None:
 
 
 @export
-class PackageMembersReferenceSymbol(Symbol):
+class PackageMemberReferenceSymbol(Symbol):
 	"""A package member reference in a use clause."""
 
 	def __init__(self, name: Name):
@@ -181,7 +181,7 @@ def Member(self, value: 'Package') -> None:  # TODO: typehint
 class AllPackageMembersReferenceSymbol(Symbol):
 	"""A package reference in a use clause."""
 
-	def __init__(self, name: Name):
+	def __init__(self, name: AllName):
 		super().__init__(name, PossibleReference.PackageMember)
 
 	@property

diff --git a/pyVHDLModel/__init__.py b/pyVHDLModel/__init__.py
@@ -64,7 +64,7 @@
 from pyVHDLModel.Exception     import ArchitectureExistsInLibraryError, PackageExistsInLibraryError, PackageBodyExistsError, ConfigurationExistsInLibraryError
 from pyVHDLModel.Exception     import ContextExistsInLibraryError, ReferencedLibraryNotExistingError
 from pyVHDLModel.Base          import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
-from pyVHDLModel.Symbol        import AllPackageMembersReferenceSymbol, PackageMembersReferenceSymbol
+from pyVHDLModel.Symbol        import AllPackageMembersReferenceSymbol, PackageMemberReferenceSymbol
 from pyVHDLModel.Concurrent    import EntityInstantiation, ComponentInstantiation, ConfigurationInstantiation
 from pyVHDLModel.DesignUnit    import DesignUnit, PrimaryUnit, Architecture, PackageBody, Context, Entity, Configuration, Package
 from pyVHDLModel.PSLModel      import VerificationUnit, VerificationProperty, VerificationMode
@@ -704,7 +704,7 @@ def LinkContexts(self) -> None:
 					if isinstance(symbol, AllPackageMembersReferenceSymbol):
 						pass
 
-					elif isinstance(symbol, PackageMembersReferenceSymbol):
+					elif isinstance(symbol, PackageMemberReferenceSymbol):
 						raise NotImplementedError()
 					else:
 						raise VHDLModelException()
@@ -848,7 +848,7 @@ def LinkPackageReferences(self) -> None:
 						for componentIdentifier, component in package._components.items():
 							designUnit._namespace._elements[componentIdentifier] = component
 
-					elif isinstance(packageMemeberSymbol, PackageMembersReferenceSymbol):
+					elif isinstance(packageMemeberSymbol, PackageMemberReferenceSymbol):
 						raise NotImplementedError()
 					else:
 						raise VHDLModelException()