Improved type hints.

pyVHDLModel/Association.py

@@ -80,7 +80,7 @@ def Formal(self) -> Nullable[Symbol]:  # TODO: can also be a conversion function
 	def Actual(self) -> ExpressionUnion:
 		return self._actual
 
-	def __str__(self):
+	def __str__(self) -> str:
 		if self._formal is None:
 			return str(self._actual)
 		else:

pyVHDLModel/Base.py

@@ -62,7 +62,7 @@ class Direction(Enum):
 	To =      0  #: Ascending direction
 	DownTo =  1  #: Descending direction
 
-	def __str__(self):
+	def __str__(self) -> str:
 		"""
 		Formats the direction to ``to`` or ``downto``.
 
@@ -88,7 +88,7 @@ class Mode(Enum):
 	Buffer =  4  #: Buffered output
 	Linkage = 5  #: undocumented
 
-	def __str__(self):
+	def __str__(self) -> str:
 		"""
 		Formats the direction.
 
@@ -109,7 +109,7 @@ class ModelEntity(metaclass=ExtendedType, slots=True):
 
 	_parent: 'ModelEntity'      #: Reference to a parent entity in the model.
 
-	def __init__(self):
+	def __init__(self) -> None:
 		"""Initializes a VHDL model entity."""
 		self._parent = None
 
@@ -285,7 +285,7 @@ class ConditionalMixin(metaclass=ExtendedType, mixin=True):
 
 	_condition: ExpressionUnion
 
-	def __init__(self, condition: ExpressionUnion = None):
+	def __init__(self, condition: ExpressionUnion = None) -> None:
 		self._condition = condition
 		if condition is not None:
 			condition._parent = self
@@ -299,7 +299,7 @@ def Condition(self) -> ExpressionUnion:
 class BranchMixin(metaclass=ExtendedType, mixin=True):
 	"""A ``BaseBranch`` is a mixin-class for all statements with branches."""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		pass
 
 
@@ -333,7 +333,7 @@ class ReportStatementMixin(metaclass=ExtendedType, mixin=True):
 	_message:  Nullable[ExpressionUnion]
 	_severity: Nullable[ExpressionUnion]
 
-	def __init__(self, message: ExpressionUnion = None, severity: ExpressionUnion = None):
+	def __init__(self, message: ExpressionUnion = None, severity: ExpressionUnion = None) -> None:
 		self._message = message
 		if message is not None:
 			message._parent = self
@@ -363,7 +363,7 @@ def __init__(self, condition: ExpressionUnion, message: ExpressionUnion = None,
 class BlockStatementMixin(metaclass=ExtendedType, mixin=True):
 	"""A ``BlockStatement`` is a mixin-class for all block statements."""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		pass
 
 

pyVHDLModel/Common.py

@@ -60,7 +60,7 @@ class Statement(ModelEntity, LabeledEntityMixin):
 	"""
 	A ``Statement`` is a base-class for all statements.
 	"""
-	def __init__(self, label: str = None):
+	def __init__(self, label: str = None) -> None:
 		super().__init__()
 		LabeledEntityMixin.__init__(self, label)
 

pyVHDLModel/Concurrent.py

@@ -112,7 +112,7 @@ def IterateInstantiations(self) -> Generator['Instantiation', None, None]:
 			yield from generate.IterateInstantiations()
 
 	# TODO: move into _init__
-	def IndexStatements(self):
+	def IndexStatements(self) -> None:
 		for statement in self._statements:
 			if isinstance(statement, (EntityInstantiation, ComponentInstantiation, ConfigurationInstantiation)):
 				self._instantiations[statement.NormalizedLabel] = statement
@@ -450,7 +450,7 @@ class GenerateStatement(ConcurrentStatement):
 
 	_namespace: Namespace
 
-	def __init__(self, label: str = None):
+	def __init__(self, label: str = None) -> None:
 		super().__init__(label)
 
 		self._namespace = Namespace(self._normalizedLabel)
@@ -664,7 +664,7 @@ def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
 		for case in self._cases:
 			yield from case.IterateInstantiations()
 
-	def IndexStatement(self):
+	def IndexStatement(self) -> None:
 		for case in self._cases:
 			case.IndexStatements()
 

pyVHDLModel/Declaration.py

@@ -107,7 +107,7 @@ def __init__(self, identifier: str, subtype: Symbol, documentation: str = None):
 		subtype._parent = self
 
 	@property
-	def Subtype(self):
+	def Subtype(self) -> None:
 		return self._subtype
 
 

pyVHDLModel/DesignUnit.py

@@ -374,7 +374,7 @@ def PackageReferences(self) -> List[UseClause]:
 	def ContextReferences(self) -> List[ContextReference]:
 		return self._contextReferences
 
-	def __str__(self):
+	def __str__(self) -> str:
 		lib = self._library.Identifier + "?" if self._library is not None else ""
 
 		return f"Context: {lib}.{self._identifier}"
@@ -482,7 +482,7 @@ def Package(self) -> PackageSymbol:
 	def DeclaredItems(self) -> List:
 		return self._declaredItems
 
-	def LinkDeclaredItemsToPackage(self):
+	def LinkDeclaredItemsToPackage(self) -> None:
 		pass
 
 	def __str__(self) -> str:

pyVHDLModel/Exception.py

@@ -51,7 +51,7 @@ class VHDLModelException(Exception):
 	# Implementing a dummy method for Python versions before
 	__notes__: List[str]
 	if version_info < (3, 11):  # pragma: no cover
-		def add_note(self, message: str):
+		def add_note(self, message: str) -> None:
 			try:
 				self.__notes__.append(message)
 			except AttributeError:

pyVHDLModel/Expression.py

@@ -568,7 +568,7 @@ class TernaryExpression(BaseExpression):
 	_secondOperand: ExpressionUnion
 	_thirdOperand:  ExpressionUnion
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		# FIXME: parameters and initializers are missing !!

pyVHDLModel/IEEE.py

@@ -78,10 +78,10 @@ class Ieee(PredefinedLibrary):
 	     * Library :class:`~pyVHDLModel.STD.Std`
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__(PACKAGES)
 
-	def LoadSynopsysPackages(self):
+	def LoadSynopsysPackages(self) -> None:
 		self.AddPackages(PACKAGES_SYNOPSYS)
 
 
@@ -106,7 +106,7 @@ class Math_Complex(PredefinedPackage):
 	Predefined package ``ieee.math_complex``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("work.math_real.all",))
@@ -118,7 +118,7 @@ class Math_Complex_Body(PredefinedPackageBody):
 	Predefined package body of package ``ieee.math_complex``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("work.math_real.all",))
@@ -135,7 +135,7 @@ class Std_logic_1164(PredefinedPackage):
 	* ``std_logic``, ``std_logic_vector``
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("STD.TEXTIO.all", ))
@@ -182,7 +182,7 @@ class std_logic_textio(PredefinedPackage):
 	Predefined package ``ieee.std_logic_textio``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("STD.TEXTIO.all", ))
@@ -196,7 +196,7 @@ class Std_logic_misc(PredefinedPackage):
 	Predefined package ``ieee.std_logic_misc``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))
@@ -216,7 +216,7 @@ class Numeric_Bit(PredefinedPackage):
 	Predefined package ``ieee.numeric_bit``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("STD.TEXTIO.all", ))
@@ -242,7 +242,7 @@ class Numeric_Bit_Unsigned_Body(PredefinedPackageBody):
 	Predefined package body of package ``ieee.numeric_bit_unsigned``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))
@@ -260,7 +260,7 @@ class Numeric_Std(PredefinedPackage):
 	* ``unresolved_signed``, ``signed``
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("STD.TEXTIO.all", ))
@@ -299,7 +299,7 @@ class Numeric_Std_Unsigned(PredefinedPackage):
 	Predefined package ``ieee.numeric_std_unsigned``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))
@@ -312,7 +312,7 @@ class Numeric_Std_Unsigned_Body(PredefinedPackageBody):
 	Predefined package body of package ``ieee.numeric_std_unsigned``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))
@@ -332,7 +332,7 @@ class Fixed_Generic_Pkg(PredefinedPackage):
 	Predefined package ``ieee.fixed_generic_pkg``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("STD.TEXTIO.all", ))
@@ -348,7 +348,7 @@ class Fixed_Generic_Pkg_Body(PredefinedPackageBody):
 	Predefined package body of package ``ieee.fixed_generic_pkg``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))
@@ -360,7 +360,7 @@ class Fixed_Pkg(PredefinedPackage):
 	"""
 	Predefined package ``ieee.fixed_pkg``.
 	"""
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))
@@ -372,7 +372,7 @@ class Float_Generic_Pkg(PredefinedPackage):
 	Predefined package ``ieee.float_generic_pkg``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddPackageClause(("STD.TEXTIO.all", ))
@@ -395,7 +395,7 @@ class Float_Pkg(PredefinedPackage):
 	Predefined package ``ieee.float_pkg``.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 
 		self._AddLibraryClause(("IEEE", ))

pyVHDLModel/Instantiation.py

@@ -48,21 +48,21 @@
 
 @export
 class GenericInstantiationMixin(metaclass=ExtendedType, mixin=True):
-	def __init__(self):
+	def __init__(self) -> None:
 		pass
 
 
 @export
 class GenericEntityInstantiationMixin(GenericInstantiationMixin, mixin=True):
-	def __init__(self):
+	def __init__(self) -> None:
 		pass
 
 
 @export
 class SubprogramInstantiationMixin(GenericInstantiationMixin, mixin=True):
 	_subprogramReference: Subprogram  # FIXME: is this a subprogram symbol?
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__()
 		self._subprogramReference = None
 

pyVHDLModel/Interface.py

@@ -50,7 +50,7 @@
 class InterfaceItemMixin(DocumentedEntityMixin, mixin=True):
 	"""An ``InterfaceItem`` is a base-class for all mixin-classes for all interface items."""
 
-	def __init__(self, documentation: str = None):
+	def __init__(self, documentation: str = None) -> None:
 		super().__init__(documentation)
 
 

pyVHDLModel/Name.py

@@ -221,7 +221,7 @@ class OpenName(Name):
 
 	Most likely this name is used in port associations.
 	"""
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__("open")  # TODO: the case of 'ALL' is not preserved
 
 	def __str__(self) -> str:

pyVHDLModel/Object.py

@@ -92,7 +92,7 @@ class WithDefaultExpressionMixin(metaclass=ExtendedType, mixin=True):
 
 	_defaultExpression: Nullable[ExpressionUnion]
 
-	def __init__(self, defaultExpression: ExpressionUnion = None):
+	def __init__(self, defaultExpression: ExpressionUnion = None) -> None:
 		self._defaultExpression = defaultExpression
 		if defaultExpression is not None:
 			defaultExpression._parent = self

pyVHDLModel/Predefined.py

@@ -57,7 +57,7 @@ def __init__(self, packages):
 
 		self.AddPackages(packages)
 
-	def AddPackages(self, packages):
+	def AddPackages(self, packages) -> None:
 		for packageType, packageBodyType in packages:
 			package: Package = packageType()
 			package.Library = self
@@ -104,7 +104,7 @@ class PredefinedPackage(Package, PredefinedPackageMixin):
 	A base-class for predefined VHDL packages.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		super().__init__(self.__class__.__name__)
 
 
@@ -114,6 +114,6 @@ class PredefinedPackageBody(PackageBody, PredefinedPackageMixin):
 	A base-class for predefined VHDL package bodies.
 	"""
 
-	def __init__(self):
+	def __init__(self) -> None:
 		packageSymbol = PackageSymbol(SimpleName(self.__class__.__name__[:-5]))
 		super().__init__(packageSymbol)