Split 'ConstrainedSubTypeSymbol' into a scalar and composite variant.

VHDL · Jun 23, 2021 · 173d53c · 173d53c
1 parent b0f4627
commit 173d53c
Showing 1 changed file with 15 additions and 1 deletion.
diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py
@@ -326,7 +326,21 @@ def __init__(self, subTypeName: str):
 
 
 @export
-class ConstrainedSubTypeSymbol(SubTypeSymbol):
+class ConstrainedScalarSubTypeSymbol(SubTypeSymbol):
+	_range: 'Range'
+
+	def __init__(self, subTypeName: str, range: 'Range' = None):
+		super().__init__(symbolName = subTypeName)
+		self._subType = None
+		self._range = range
+
+	@property
+	def Range(self) -> 'Range':
+		return self._range
+
+
+@export
+class ConstrainedCompositeSubTypeSymbol(SubTypeSymbol):
 	_constraints: List[Constraint]
 
 	def __init__(self, subTypeName: str, constraints: List[Constraint] = None):