Appendix typos

X16 Reference - Appendix A - Sound.md

@@ -250,7 +250,7 @@ On the YM2151 using channel 0, plays in the current octave the sequence **C** **
 
 
 ### Octave
-* Synopsis: Explictly set the octave number for notes that follow
+* Synopsis: Explicitly set the octave number for notes that follow
 * Syntax: `O<0-7>`
 
 Example:

X16 Reference - Appendix C - 65C02 Processor.md

@@ -12,7 +12,7 @@ The WDC65C02 CPU is a modern version of the MOS6502 with a few additional
 instructions and addressing modes and is capable of running at up to 14 MHz. On
 the Commander X16, it is clocked at 8 MHz.
 
-## A note about 65C816 Compatibilty
+## A note about 65C816 Compatibility
 
 The Commander X16 may be upgraded at some point to use the WDC 65C816 CPU.
 The 65C816 is mostly compatible with the 65C02, except for 4 instructions
@@ -137,7 +137,7 @@ AND ($20)    ZP Indirect    $32   2     5     N-----Z- +c
 
 Bitwise AND the provided value with the Accumulator.
 
-- Sets N (Negative) flag if the bit 7 of the result is 1, and otherewise
+- Sets N (Negative) flag if the bit 7 of the result is 1, and otherwise
 clears it.
 - Sets Z (Zero) is the result is zero, and otherwise clears it  
 
@@ -289,7 +289,7 @@ BIT $8080,X  Absolute,X     $3C   3     4+    NV----Z- +c +p
 
 - Sets Z (Zero) flag based on an AND of value provided to the Accumulator.
 - Sets N (Negative) flag to the value of bit 7 at the provided address (NOTE: not with immediate).
-- Sets V (Overflow) flag to the value of bit 6 at the provided addres (NOTE: not with immediate).
+- Sets V (Overflow) flag to the value of bit 6 at the provided address (NOTE: not with immediate).
 
 +p: Add 1 cycle if a page boundary is crossed when forming address.  
 +c: New for the 65C02  
@@ -541,7 +541,7 @@ leaving the new value in its place.
 
 #### 16-bit DEC Example
 
-You can peform a 16-bit DEC by chaining two DECs together, testing the low
+You can perform a 16-bit DEC by chaining two DECs together, testing the low
 byte before decrementing the high byte:
 
 ```asm
@@ -633,7 +633,7 @@ new value in its place.
 
 #### 16-bit INC Example
 
-You can peform a 16-bit INC by chaining two INCs together, testing the low
+You can perform a 16-bit INC by chaining two INCs together, testing the low
 byte after incrementing it.
 
 ```asm
@@ -1311,7 +1311,7 @@ TSB $8080    Absolute       $0C   3     5     ------Z- +c
 
 Performs an OR with each bit in the accumulator and memory.
 Each bit that is 1 in the Accumulator is set to 1 in memory. This is similar to
-an ORA operation, execpt that the result is stored in memory, not in A.
+an ORA operation, except that the result is stored in memory, not in A.
 
 The Z flag is set based on the final result of the operation, ie: the memory
 data is 0.
@@ -1335,7 +1335,7 @@ TSX          Implied        $BA   1     2     N-----Z- Copy from Stack Pointer t
 TXS          Implied        $9A   1     2     -------- Copy from .X to Stack Pointer
 ```
 
-Copies data from one register to anohter.
+Copies data from one register to another.
 
 TSX and TSX copy between the Stack Pointer and the X register. This is the only
 way to directly control the Stack Pointer. To initialize the Stack Pointer to
@@ -1358,7 +1358,7 @@ SYNTAX       MODE           HEX  LEN  CYCLES  FLAGS
 WAI          Implied        $CB   1     3     -------- +c
 ```
 
-Effectively stops the processor until a hardware interrupt occurs. The intterupt
+Effectively stops the processor until a hardware interrupt occurs. The interrupt
 is processed immediately, and execution resumes in the Interrupt handler.
 
 NMI, IRQ, and RST (Reset) will recover from the WAI condition.
@@ -1388,7 +1388,7 @@ P-Register:
   1 = Always 1  
   B = Interrupt Flag  
   D = Decimal Mode  
-  I = Interupts Disabled  
+  I = Interrupts Disabled  
   Z = Zero  
   C = Carry  
 

X16 Reference - Appendix D - Official Expansion Cards.md

@@ -6,15 +6,15 @@ This is just a stub as a proposal for how to document official expansion cards
 
 ## Serial/MIDI UART/Wavetable Expansion Card
 
-Kevin is desinging an EIA compliant UART expansion card which is capable of supporting 
+Kevin is designing an EIA compliant UART expansion card which is capable of supporting 
 standard serial as well as MIDI and even has a header to install wavetable cards.
 It uses the Texas Instruments [TL16C2550](https://www.ti.com/product/TL16C2550).
 
 ![Prototype Serial Card](images/Appendix_B/X16-Serial.png)
 
 As the card is still in development there are not any demos or code examples available,
-though the datasheet contains informaiton on how to set things up (see below). Kevin
-also provied [some information](https://discord.com/channels/547559626024157184/548715649065811989/1183801692878295101) on how to setup the card in his original announcement on the community Discord.
+though the datasheet contains information on how to set things up (see below). Kevin
+also provided [some information](https://discord.com/channels/547559626024157184/548715649065811989/1183801692878295101) on how to set up the card in his original announcement on the community Discord.
 
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X16 Reference - Appendix E - Diagnostic Bank.md

@@ -28,7 +28,7 @@ It is also possible to jump directly to the diagnostic ROM bank from assembly.
 	jmp	$C000   ; Jump to beginning of diagnostic ROM
 ```  
 
-NOTE: The Diagnostic ROM is not able to return to BASIC or any program that has called. The only way to exit the Diagnostic ROM is by resetting or powercycling the system.
+NOTE: The Diagnostic ROM is not able to return to BASIC or any program that has called. The only way to exit the Diagnostic ROM is by resetting or power cycling the system.
 ### Non functional system
 If the Commander X16 is not able to boot into BASIC, the memory diagnostics can be started by keeping the power button pressed for about a second when powering on the system.  
 This will make the Commander X16 boot directly into the diagnostic ROM bank and start the memory diagnostics.
@@ -42,7 +42,7 @@ When the diagnostic ROM bank starts, it will use the activity LED to indicate th
 * OFF - for 3rd test of base memory ($0100-$9EFF)
 * ON - for 4th test of base memory ($0100-$9EFF)
 
-After the inital test of base memory, the number of available memory banks is tested, VERA is initialized and both the activity LED and the keyboard LEDs are used to indicate the progress.  
+After the initial test of base memory, the number of available memory banks is tested, VERA is initialized and both the activity LED and the keyboard LEDs are used to indicate the progress.  
 The keyboard LEDs are used as a binary counter:  
 | Num | Binary | Num Lock | Caps Lock | Scroll Lock |
 |-----|--------|----------|-----------|-------------|
@@ -58,7 +58,7 @@ The keyboard LEDs are used as a binary counter:
 #### Main test loop
 During the first test iteration, the keyboard LEDs will display 0 0 1  
 When the test is done, the activity light will blink once.  
-During the second test iteration, the keyboard LEDS will display 0 1 0  
+During the second test iteration, the keyboard LEDs will display 0 1 0  
 When the test is done, the activity light will blink once.  
 During the third test iteration, the keyboard LEDs will display 0 1 1  
 When the test is done, the activity light will blink once.  
@@ -81,14 +81,14 @@ When the initial test of base memory has succeeded and VERA is initialized, any
 
 Even when tests are stopped, VERA output will still be switched between VGA and Composite/S-Video about every minute.
 
-The errorcodes on screen are as follows:
-![Errorcode definition](images/Appendix_E/mem-diag-error-code.jpg)
+The error codes on screen are as follows:
+![Error code definition](images/Appendix_E/mem-diag-error-code.jpg)
 
 ## Test algorithm
 ### Theory
-RAM diagnostics are performed with the March C- algorithm. This algorithm should be fairly godd at finding most common memory errors.  
+RAM diagnostics are performed with the March C- algorithm. This algorithm should be fairly good at finding most common memory errors.  
 
-In short, he aslgorithm is described as follows:
+In short, the algorithm is described as follows:
 1. Write 0 to all memory cells
 2. For each cell, check that it contains 0 and write 1 in ascending order
 3. For each cell, check that it contains 1 and write 0 in ascending order
@@ -105,21 +105,21 @@ To catch most memory errors, the following bit patterns are tested:
 
 The algorithm is then implemented in the following way:
 1. Write pattern to all memory addresses
-2. For each addres, check the patterna and write the inverted patterin in ascending order
+2. For each address, check the pattern and write the inverted pattern in ascending order
 3. For each address, check the inverted pattern and write the original pattern in ascending order
 4. For each address, check the original pattern and write the inverted pattern in descending order
 5. For eac address, check the inverted pattern and write the original pattern in descending order
 6. Check all addresses contain the original pattern
 ### Implementation
-When memory test starts, the first thing that happens is that zero-page is tested by it self. If this test passes, the rest of base memory is tested from $0100-$9EFF while ensuring that these tests do not affect zero-page memory.  
+When memory test starts, the first thing that happens is that zero-page is tested by itself. If this test passes, the rest of base memory is tested from $0100-$9EFF while ensuring that these tests do not affect zero-page memory.  
 
-When basememory has passed the initial test, zero-page is used for variables and stack pointer is initialized to enable pushing and popping of registers and function calls.  
+When base memory has passed the initial test, zero-page is used for variables and stack pointer is initialized to enable pushing and popping of registers and function calls.  
 VERA is initialized and the number of memory banks is tested.  
 
 All available memory banks are tested together as opposed to checking and clearing a single memory page at a time.  
 When all memory banks have been tested, the base memory $0200-$9EFF is tested again.  
 
-Memory banks and base memory is tested in continous loop.  
+Memory banks and base memory is tested in continuous loop.  
 
 If an error is detected, this is either communicated through the activity LED, if VERA has not yet been initialized, or by writing information about the error on the display.
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