Merge pull request #1044 from Xilinx/bugfix/FIFO_countrange

Bug fix for FIFO count range mismatch between Python and RTL

finn-rtllib/fifo/hdl/Q_srl.v

@@ -74,7 +74,8 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
    parameter depth = 16;   // - greatest #items in queue  (2 <= depth <= 256)
    parameter width = 16;   // - width of data (i_d, o_d)
 
-   parameter addrwidth = $clog2(depth);
+   localparam countwidth = $clog2(depth + 1);
+   localparam addrwidth = $clog2(depth);
 
    input     clock;
    input     reset;
@@ -89,10 +90,10 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
    input              o_r;	// - output stream ready
    wire               o_b;	// - output stream back-pressure
 
-   output [addrwidth:0] count;  // - output number of elems in queue
-   output [addrwidth:0] maxcount;  // - maximum observed count since reset
+   output [countwidth-1:0] count;  // - output number of elems in queue
+   output [countwidth-1:0] maxcount;  // - maximum observed count since reset
 
-   reg [addrwidth:0] maxcount_reg;  // - maximum count seen until now
+   reg [countwidth-1:0] maxcount_reg;  // - maximum count seen until now
    reg    [addrwidth-1:0] addr, addr_, a_;		// - SRL16 address
 							//     for data output
    reg 			  shift_en_;			// - SRL16 shift enable

src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py

@@ -95,7 +95,7 @@ def generate_hdl(self, model, fpgapart, clk):
         code_gen_dict["$TOP_MODULE_NAME$"] = topname
         # make instream width a multiple of 8 for axi interface
         in_width = self.get_instream_width_padded()
-        count_width = int(self.get_nodeattr("depth") - 1).bit_length()
+        count_width = int(self.get_nodeattr("depth")).bit_length()
         code_gen_dict["$COUNT_RANGE$"] = "[{}:0]".format(count_width - 1)
         code_gen_dict["$IN_RANGE$"] = "[{}:0]".format(in_width - 1)
         code_gen_dict["$OUT_RANGE$"] = "[{}:0]".format(in_width - 1)