Raise error for FIFO depth smaller than two.

Xilinx · Feb 25, 2025 · 9d7989b · 9d7989b
1 parent 706ce54
commit 9d7989b
Showing 1 changed file with 9 additions and 0 deletions.
diff --git a/finn-rtllib/fifo/hdl/Q_srl.v b/finn-rtllib/fifo/hdl/Q_srl.v
@@ -119,6 +119,15 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
    reg       i_b_reg  		    // - true iff !full
 	     /* synthesis syn_allow_retiming=0 */ ;
 
+	// Parameter Checking
+	initial begin
+		if(depth < 2) begin
+			$error("%m: FIFO depth must be two or higher.");
+			$finish;
+		end
+	end
+
+
    assign addr_full_ = (state_==state_more) && (addr_==depth-2);
 						// - queue full
    assign addr_zero_ = (addr==0);		// - queue contains 2 (or 1,0)