[AIE] Legalize G_AND for <8 x s64> vector.

Xilinx · Jan 19, 2025 · be1e22b · be1e22b
1 parent 03cece6
commit be1e22b
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Showing 3 changed files with 32 additions and 0 deletions.
diff --git a/llvm/lib/Target/AIE/AIE2LegalizerInfo.cpp b/llvm/lib/Target/AIE/AIE2LegalizerInfo.cpp
@@ -216,6 +216,13 @@ AIE2LegalizerInfo::AIE2LegalizerInfo(const AIE2Subtarget &ST) : AIEHelper(ST) {
   getActionDefinitionsBuilder({G_AND, G_OR})
       .legalFor({S32})
       .legalFor(AIE2VectorTypes)
+      .bitcastIf(
+          [=](const LegalityQuery &Query) {
+            return Query.Types[0] == LLT::fixed_vector(8, 64);
+          },
+          [=](const LegalityQuery &Query) {
+            return std::pair(0, LLT::fixed_vector(16, 32));
+          })
       .widenScalarToNextPow2(0)
       .clampScalar(0, S32, S32);
 

diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp b/llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp
@@ -255,6 +255,13 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST)
   getActionDefinitionsBuilder({G_AND, G_OR})
       .legalFor({S32})
       .legalFor(AIE2PVectorTypes)
+      .bitcastIf(
+          [=](const LegalityQuery &Query) {
+            return Query.Types[0] == LLT::fixed_vector(8, 64);
+          },
+          [=](const LegalityQuery &Query) {
+            return std::pair(0, LLT::fixed_vector(16, 32));
+          })
       .widenScalarToNextPow2(0)
       .clampScalar(0, S32, S32);
 

diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-and.mir
@@ -195,6 +195,24 @@ body:             |
     PseudoRET implicit $lr, implicit %2
 ...
 
+---
+name:            and_vec_8xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: and_vec_8xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s64>) = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s64>) = COPY $x1
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[COPY]](<8 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[COPY1]](<8 x s64>)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<8 x s64>) = G_BITCAST [[AND]](<16 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST2]](<8 x s64>)
+    %0:_(<8 x s64>) = COPY $x0
+    %1:_(<8 x s64>) = COPY $x1
+    %2:_(<8 x s64>) = G_AND %0(<8 x s64>), %1(<8 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
+
 ---
 name:            and_vec_1024
 body:             |