[AIE2] Fix missing bypass for VMOV to Q registers

Xilinx · Dec 12, 2024 · e1a7618 · e1a7618
1 parent 6caf5f2
commit e1a7618
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Showing 3 changed files with 36 additions and 1 deletion.
diff --git a/llvm/lib/Target/AIE/AIE2GenFixupInstrInfo.td b/llvm/lib/Target/AIE/AIE2GenFixupInstrInfo.td
@@ -762,7 +762,9 @@ let Itinerary = II_VMOV_W in {
                            ItinRegClassPair<II_VMOV_W_WMH_WML,[OperandRegClass<0, eWH>, OperandRegClass<1, eWL>]>,						   
                            ItinRegClassPair<II_VMOV_W_WML_WMH,[OperandRegClass<0, eWL>, OperandRegClass<1, eWH>]>,
                            ItinRegClassPair<II_VMOV_W_WML_Q, [OperandRegClass<0, eWL>, OperandRegClass<1, mQQm>]>,
-                           ItinRegClassPair<II_VMOV_W_WMH_Q, [OperandRegClass<0, eWH>, OperandRegClass<1, mQQm>]>] in {	
+                           ItinRegClassPair<II_VMOV_W_WMH_Q, [OperandRegClass<0, eWH>, OperandRegClass<1, mQQm>]>,
+                           ItinRegClassPair<II_VMOV_W_Q_WML, [OperandRegClass<0, mQQm>, OperandRegClass<1, eWL>]>,
+                           ItinRegClassPair<II_VMOV_W_Q_WMH, [OperandRegClass<0, mQQm>, OperandRegClass<1, eWH>]>] in {	
 	def VMOV_mv_w : AIE2_mv_w_inst_mv< (outs OP_mMvAMWQDst:$dst), (ins OP_mMvAMWQSrc:$src),
 		"vmov", "$dst, $src">;
   }

diff --git a/llvm/lib/Target/AIE/AIE2Schedule.td b/llvm/lib/Target/AIE/AIE2Schedule.td
@@ -350,6 +350,8 @@ def II_VMOV_W_WMH_WML : InstrItinClass;
 def II_VMOV_W_WML_WML : InstrItinClass;
 def II_VMOV_W_WML_Q : InstrItinClass;
 def II_VMOV_W_WMH_Q : InstrItinClass;
+def II_VMOV_W_Q_WML : InstrItinClass;
+def II_VMOV_W_Q_WMH : InstrItinClass;
 def II_VMOV_X : InstrItinClass;
 def II_VMOV_X_BM_BM : InstrItinClass;
 def II_VMOV_X_BM_XM : InstrItinClass;
@@ -999,6 +1001,10 @@ InstrItinData<II_VMOV_W_WML_Q, [EmptyCycles<1>, SimpleCycle<W_WM_PORT>],
               [2,1], [MOV_Bypass, NoBypass]>,
 InstrItinData<II_VMOV_W_WMH_Q, [EmptyCycles<1>, SimpleCycle<W_WM_PORT>],
               [2,1], [NoBypass, NoBypass]>,
+InstrItinData<II_VMOV_W_Q_WML, [EmptyCycles<1>, SimpleCycle<W_WM_PORT>],
+              [2,1], [NoBypass, MOV_Bypass]>,
+InstrItinData<II_VMOV_W_Q_WMH, [EmptyCycles<1>, SimpleCycle<W_WM_PORT>],
+              [2,1], [NoBypass, NoBypass]>,
 InstrItinData<II_VMOV_X, [SimpleCycle<CM_RM_PORT>, PrefixCycle<W_WM_PORT>, SimpleCycle<CM_WM_PORT>],
               [2,1], [NoBypass, NoBypass]>,
 InstrItinData<II_VMOV_X_BM_BM, [SimpleCycle<CM_RM_PORT>, SimpleCycle<CM_WM_PORT>],

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/mov_bypass.mir b/llvm/test/CodeGen/AIE/aie2/schedule/mov_bypass.mir
@@ -148,6 +148,33 @@ body:             |
     $wl0 = VMOV_mv_w $wh1
 ...
 
+---
+name:            bypass_q_wl
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: bypass_q_wl
+    ; CHECK: $wl1 = VMOV_mv_w killed $wl0
+    ; CHECK-NEXT: $q0 = VMOV_mv_w killed $wl1
+    ; CHECK-NEXT: NOP
+    $wl1 = VMOV_mv_w $wl0
+    $q0 = VMOV_mv_w $wl1
+...
+
+---
+name:            no_bypass_q_wh
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: no_bypass_q_wh
+    ; CHECK: $wh1 = VMOV_mv_w killed $wl0
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: $q0 = VMOV_mv_w killed $wh1
+    ; CHECK-NEXT: NOP
+    $wh1 = VMOV_mv_w $wl0
+    $q0 = VMOV_mv_w $wh1
+...
+
 ---
 name:            bypass_x
 alignment:       16