[AIE2] Fix VMOV instruction itinerary #239
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krishnamtibrewala
requested review from
abhinay-anubola,
abnikant,
andcarminati,
gbossu,
khallouh,
konstantinschwarz,
martien-de-jong,
SagarMaheshwari99 and
stephenneuendorffer
as code owners
gbossu
reviewed
Nov 19, 2024
| ItinRegClassPair<II_VMOV_W_WML_WMH,[OperandRegClass<0, eWL>, OperandRegClass<1, eWH>]>] in { | ||
| ItinRegClassPair<II_VMOV_W_WML_WMH,[OperandRegClass<0, eWL>, OperandRegClass<1, eWH>]>, | ||
| ItinRegClassPair<II_VMOV_W_WML_Q, [OperandRegClass<0, eWL>, OperandRegClass<1, mQQm>]>, | ||
| ItinRegClassPair<II_VMOV_W_WMH_Q, [OperandRegClass<0, eWH>, OperandRegClass<1, mQQm>]>] in { | ||
| def VMOV_mv_w : AIE2_mv_w_inst_mv< (outs OP_mMvAMWQDst:$dst), (ins OP_mMvAMWQSrc:$src), |
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Could you think of an easy way to check that the II_VMOV_W itinerary is never used by the postmisched? Doing so can result in problems like the one you describe. Maybe in getSchedClass we should assert if we fallback to the default itinerary because none of the operands matched?
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| name: no_bypass_wl_q |
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Do you mean no_bypass_wh_q?
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Changes done in this PR were identified by @konstantinschwarz for fixing the DIFF issue in FullyConnect_aie2_bf16
ISSUE : In a specific case the compiler was assuming that VMOV has a latency of 2, i.e. it can still use the old value of $wlX when written from $qX reg, but since the DST reg was of $wlX type which uses the bypass path and overwrites the value one cycle earlier, leading to wrong value being read.