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Merge pull request #174 from Xilinx/bump_to_693ba938
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[AutoBump] Merge with fixes of 693ba93 (Jun 17) (10) (needs LLVM bump Jun 11)
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cferry-AMD authored Sep 12, 2024
2 parents 23c5025 + c7074d4 commit c0033eb
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Showing 11 changed files with 43 additions and 68 deletions.
2 changes: 1 addition & 1 deletion docs/BuildOnLinuxOSX.md
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Expand Up @@ -15,7 +15,7 @@ Firstly, install MLIR (as a part of LLVM-Project):
``` bash
git clone -n https://github.com/llvm/llvm-project.git
# Check out a specific branch that is known to work with ONNX-MLIR.
cd llvm-project && git checkout 765206e050453018e861637a08a4520f29238074 && cd ..
cd llvm-project && git checkout c012e487b7246239c31bd378ab074fb110631186 && cd ..
```

[same-as-file]: <> (utils/build-mlir.sh)
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2 changes: 1 addition & 1 deletion docs/BuildOnWindows.md
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Expand Up @@ -52,7 +52,7 @@ Install MLIR (as a part of LLVM-Project):
```shell
git clone -n https://github.com/llvm/llvm-project.git
# Check out a specific branch that is known to work with ONNX-MLIR.
cd llvm-project && git checkout 765206e050453018e861637a08a4520f29238074 && cd ..
cd llvm-project && git checkout c012e487b7246239c31bd378ab074fb110631186 && cd ..
```

[same-as-file]: <> (utils/build-mlir.cmd)
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6 changes: 3 additions & 3 deletions src/Dialect/Mlir/IndexExpr.cpp
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Expand Up @@ -4,7 +4,7 @@

//===----------------IndexExpr.cpp - Index expression---------------------=== //
//
// copyright 2020-2023 The IBM Research Authors.
// copyright 2020-2024 The IBM Research Authors.
//
// =============================================================================
//
Expand All @@ -22,11 +22,11 @@
#include "mlir/Dialect/MemRef/IR/MemRef.h"
#include "mlir/IR/Operation.h"
#include "mlir/Support/LLVM.h"
#include "mlir/Support/MathExtras.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"

#define DEBUG_TYPE "index-expr"

Expand Down Expand Up @@ -947,7 +947,7 @@ IndexExpr IndexExpr::ceilDiv(IndexExpr const b) const {
// Int operator
IndexExpr IndexExpr::operator%(IndexExpr const b) const {
F2 litFct = [](IndexExpr const aa, IndexExpr const bb) -> IndexExpr {
int64_t rval = mlir::mod(aa.getLiteral(), bb.getLiteral());
int64_t rval = llvm::mod(aa.getLiteral(), bb.getLiteral());
return LiteralIndexExpr(rval);
};
F2 affineExprFct = [](IndexExpr const aa, IndexExpr const bb) -> IndexExpr {
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3 changes: 1 addition & 2 deletions src/Dialect/Mlir/IndexExprDetail.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
//===---------------IndexExprDetail.hpp - Index expression details---------===
////
//
// Copyright 2020-2023 The IBM Research Authors.
// Copyright 2020-2024 The IBM Research Authors.
//
// =============================================================================
//
Expand All @@ -19,7 +19,6 @@
#include "mlir/Dialect/Affine/IR/AffineOps.h"
#include "mlir/Dialect/Func/IR/FuncOps.h"
#include "mlir/Support/LLVM.h"
#include "mlir/Support/MathExtras.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/TypeSwitch.h"
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Expand Up @@ -72,15 +72,12 @@ module attributes {"onnx-mlir.symbol-postfix" = "tag_symbols"} {
// CHECK: [[VAR_7_1_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_6_3_]], [[VAR_4_3_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_8_1_:%.+]] = llvm.icmp "eq" [[VAR_7_1_]], [[VAR_5_4_]] : i32
// CHECK: llvm.cond_br [[VAR_8_1_]], ^bb1([[VAR_3_5_]] : !llvm.ptr), ^bb2
// CHECK: ^bb1([[VAR_9_:%.+]]: !llvm.ptr): // 2 preds: ^bb0, ^bb2
// CHECK: ^bb1([[VAR_9_:%.+]]: !llvm.ptr): // 3 preds: ^bb0, ^bb2, ^bb2
// CHECK: llvm.return [[VAR_9_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_10_1_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_2_5_]], [[VAR_1_5_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_11_1_:%.+]] = llvm.icmp "eq" [[VAR_10_1_]], [[VAR_5_4_]] : i32
// CHECK: llvm.cond_br [[VAR_11_1_]], ^bb1([[VAR_0_7_]] : !llvm.ptr), ^bb3
// CHECK: ^bb3: // pred: ^bb2
// CHECK: [[VAR_12_1_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.return [[VAR_12_1_]] : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_11_1_]], ^bb1([[VAR_0_7_]] : !llvm.ptr)
// CHECK: }

// CHECK: llvm.func @omInputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
Expand All @@ -99,15 +96,12 @@ module attributes {"onnx-mlir.symbol-postfix" = "tag_symbols"} {
// CHECK: [[VAR_7_2_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_6_4_]], [[VAR_4_4_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_8_2_:%.+]] = llvm.icmp "eq" [[VAR_7_2_]], [[VAR_5_5_]] : i32
// CHECK: llvm.cond_br [[VAR_8_2_]], ^bb1([[VAR_3_6_]] : !llvm.ptr), ^bb2
// CHECK: ^bb1([[VAR_9_]]: !llvm.ptr): // 2 preds: ^bb0, ^bb2
// CHECK: ^bb1([[VAR_9_]]: !llvm.ptr): // 3 preds: ^bb0, ^bb2, ^bb2
// CHECK: llvm.return [[VAR_9_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_10_2_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_2_6_]], [[VAR_1_6_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_11_2_:%.+]] = llvm.icmp "eq" [[VAR_10_2_]], [[VAR_5_5_]] : i32
// CHECK: llvm.cond_br [[VAR_11_2_]], ^bb1([[VAR_0_9_]] : !llvm.ptr), ^bb3
// CHECK: ^bb3: // pred: ^bb2
// CHECK: [[VAR_12_2_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.return [[VAR_12_2_]] : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_11_2_]], ^bb1([[VAR_0_9_]] : !llvm.ptr)
// CHECK: }
// CHECK: llvm.func @omOutputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
// CHECK: [[VAR_0_9_:%.+]] = llvm.call @omOutputSignature_tag_symbols([[arg0_]]) : (!llvm.ptr) -> !llvm.ptr
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Original file line number Diff line number Diff line change
Expand Up @@ -72,15 +72,12 @@ module attributes {"onnx-mlir.symbol-postfix" = "tag_symbols"} {
// CHECK: [[VAR_7_1_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_6_3_]], [[VAR_4_3_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_8_1_:%.+]] = llvm.icmp "eq" [[VAR_7_1_]], [[VAR_5_4_]] : i32
// CHECK: llvm.cond_br [[VAR_8_1_]], ^bb1([[VAR_3_5_]] : !llvm.ptr), ^bb2
// CHECK: ^bb1([[VAR_9_:%.+]]: !llvm.ptr): // 2 preds: ^bb0, ^bb2
// CHECK: ^bb1([[VAR_9_:%.+]]: !llvm.ptr): // 3 preds: ^bb0, ^bb2, ^bb2
// CHECK: llvm.return [[VAR_9_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_10_1_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_2_5_]], [[VAR_1_5_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_11_1_:%.+]] = llvm.icmp "eq" [[VAR_10_1_]], [[VAR_5_4_]] : i32
// CHECK: llvm.cond_br [[VAR_11_1_]], ^bb1([[VAR_0_7_]] : !llvm.ptr), ^bb3
// CHECK: ^bb3: // pred: ^bb2
// CHECK: [[VAR_12_1_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.return [[VAR_12_1_]] : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_11_1_]], ^bb1([[VAR_0_7_]] : !llvm.ptr)
// CHECK: }

// CHECK: llvm.func @omInputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
Expand All @@ -99,15 +96,12 @@ module attributes {"onnx-mlir.symbol-postfix" = "tag_symbols"} {
// CHECK: [[VAR_7_2_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_6_4_]], [[VAR_4_4_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_8_2_:%.+]] = llvm.icmp "eq" [[VAR_7_2_]], [[VAR_5_5_]] : i32
// CHECK: llvm.cond_br [[VAR_8_2_]], ^bb1([[VAR_3_6_]] : !llvm.ptr), ^bb2
// CHECK: ^bb1([[VAR_9_]]: !llvm.ptr): // 2 preds: ^bb0, ^bb2
// CHECK: ^bb1([[VAR_9_]]: !llvm.ptr): // 3 preds: ^bb0, ^bb2, ^bb2
// CHECK: llvm.return [[VAR_9_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_10_2_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_2_6_]], [[VAR_1_6_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_11_2_:%.+]] = llvm.icmp "eq" [[VAR_10_2_]], [[VAR_5_5_]] : i32
// CHECK: llvm.cond_br [[VAR_11_2_]], ^bb1([[VAR_0_9_]] : !llvm.ptr), ^bb3
// CHECK: ^bb3: // pred: ^bb2
// CHECK: [[VAR_12_2_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.return [[VAR_12_2_]] : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_11_2_]], ^bb1([[VAR_0_9_]] : !llvm.ptr)
// CHECK: }
// CHECK: llvm.func @omOutputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
// CHECK: [[VAR_0_9_:%.+]] = llvm.call @omOutputSignature_tag_symbols([[arg0_]]) : (!llvm.ptr) -> !llvm.ptr
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44 changes: 18 additions & 26 deletions test/mlir/conversion/krnl_to_llvm/entry_point.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -18,12 +18,12 @@ module {
// CHECK: {{.*}} = llvm.call @omTensorListGetOmtArray([[ARG0]]) : (!llvm.ptr) -> !llvm.ptr

// CHECK: llvm.mlir.global internal constant @_entry_point_arrays() {addr_space = 0 : i32} : !llvm.array<2 x ptr> {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[VAR_0_3_:%.+]] = llvm.mlir.addressof @_entry_point_0 : !llvm.ptr
// CHECK-DAG: [[VAR_1_3_:%.+]] = llvm.mlir.undef : !llvm.array<2 x ptr>
// CHECK-NOT: separator of consecutive DAGs
// CHECK-DAG: [[VAR_2_3_:%.+]] = llvm.insertvalue [[VAR_0_3_]], [[VAR_1_3_]][0] : !llvm.array<2 x ptr>
// CHECK-DAG: [[VAR_3_3_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: [[VAR_4_2_:%.+]] = llvm.insertvalue [[VAR_3_3_]], [[VAR_2_3_]][1] : !llvm.array<2 x ptr>
// CHECK: [[VAR_4_2_:%.+]] = llvm.insertvalue [[VAR_0]], [[VAR_2_3_]][1] : !llvm.array<2 x ptr>
// CHECK: llvm.return [[VAR_4_2_]] : !llvm.array<2 x ptr>
// CHECK: }

Expand All @@ -41,32 +41,28 @@ module {
// CHECK: }

// CHECK: llvm.func @omInputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[VAR_0_5_:%.+]] = llvm.mlir.addressof @_entry_point_0_in_sig : !llvm.ptr
// CHECK-DAG: [[VAR_1_5_:%.+]] = llvm.mlir.constant(15 : i64) : i64
// CHECK-DAG: [[VAR_2_5_:%.+]] = llvm.mlir.constant(0 : i32) : i32
// CHECK-DAG: [[VAR_3_5_:%.+]] = llvm.mlir.addressof @_entry_point_0 : !llvm.ptr
// CHECK: [[VAR_4_3_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_3_5_]], [[VAR_1_5_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_5_3_:%.+]] = llvm.icmp "eq" [[VAR_4_3_]], [[VAR_2_5_]] : i32
// CHECK: llvm.cond_br [[VAR_5_3_]], ^bb1, ^bb2
// CHECK: ^bb1: // pred: ^bb0
// CHECK: llvm.return [[VAR_0_5_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_6_2_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_5_3_]], ^bb1([[VAR_0_5_]] : !llvm.ptr), ^bb1([[VAR_0]] : !llvm.ptr)
// CHECK: ^bb1([[VAR_6_2_:%.+]]: !llvm.ptr): // 2 preds: ^bb0, ^bb0
// CHECK: llvm.return [[VAR_6_2_]] : !llvm.ptr
// CHECK: }

// CHECK: llvm.func @omOutputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[VAR_0_6_:%.+]] = llvm.mlir.addressof @_entry_point_0_out_sig : !llvm.ptr
// CHECK-DAG: [[VAR_1_6_:%.+]] = llvm.mlir.constant(15 : i64) : i64
// CHECK-DAG: [[VAR_2_6_:%.+]] = llvm.mlir.constant(0 : i32) : i32
// CHECK-DAG: [[VAR_3_6_:%.+]] = llvm.mlir.addressof @_entry_point_0 : !llvm.ptr
// CHECK: [[VAR_4_4_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_3_6_]], [[VAR_1_6_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_5_4_:%.+]] = llvm.icmp "eq" [[VAR_4_4_]], [[VAR_2_6_]] : i32
// CHECK: llvm.cond_br [[VAR_5_4_]], ^bb1, ^bb2
// CHECK: ^bb1: // pred: ^bb0
// CHECK: llvm.return [[VAR_0_6_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_6_3_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_5_4_]], ^bb1([[VAR_0_6_]] : !llvm.ptr), ^bb1([[VAR_0]] : !llvm.ptr)
// CHECK: ^bb1([[VAR_6_3_:%.+]]: !llvm.ptr): // 2 preds: ^bb0, ^bb0
// CHECK: llvm.return [[VAR_6_3_]] : !llvm.ptr
// CHECK: }
}
Expand Down Expand Up @@ -99,13 +95,13 @@ module {
// CHECK: {{.*}} = llvm.call @omTensorListGetOmtArray([[ARG0]]) : (!llvm.ptr) -> !llvm.ptr

// CHECK: llvm.mlir.global internal constant @_entry_point_arrays() {addr_space = 0 : i32} : !llvm.array<3 x ptr> {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[VAR_0_11_:%.+]] = llvm.mlir.addressof @_entry_point_1 : !llvm.ptr
// CHECK-DAG: [[VAR_1_13_:%.+]] = llvm.mlir.addressof @_entry_point_0 : !llvm.ptr
// CHECK-DAG: [[VAR_2_13_:%.+]] = llvm.mlir.undef : !llvm.array<3 x ptr>
// CHECK: [[VAR_3_13_:%.+]] = llvm.insertvalue [[VAR_1_13_]], [[VAR_2_13_]][0] : !llvm.array<3 x ptr>
// CHECK-DAG: [[VAR_4_9_:%.+]] = llvm.insertvalue [[VAR_0_11_]], [[VAR_3_13_]][1] : !llvm.array<3 x ptr>
// CHECK-DAG: [[VAR_5_11_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: [[VAR_6_8_:%.+]] = llvm.insertvalue [[VAR_5_11_]], [[VAR_4_9_]][2] : !llvm.array<3 x ptr>
// CHECK: [[VAR_6_8_:%.+]] = llvm.insertvalue [[VAR_0]], [[VAR_4_9_]][2] : !llvm.array<3 x ptr>
// CHECK: llvm.return [[VAR_6_8_]] : !llvm.array<3 x ptr>
// CHECK: }

Expand All @@ -123,6 +119,7 @@ module {
// CHECK: }

// CHECK: llvm.func @omInputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[VAR_0_13_:%.+]] = llvm.mlir.addressof @_entry_point_1_in_sig : !llvm.ptr
// CHECK-DAG: [[VAR_1_15_:%.+]] = llvm.mlir.constant(17 : i64) : i64
// CHECK-DAG: [[VAR_2_15_:%.+]] = llvm.mlir.addressof @_entry_point_1 : !llvm.ptr
Expand All @@ -133,18 +130,16 @@ module {
// CHECK: [[VAR_7_3_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_6_9_]], [[VAR_4_10_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_8_3_:%.+]] = llvm.icmp "eq" [[VAR_7_3_]], [[VAR_5_12_]] : i32
// CHECK: llvm.cond_br [[VAR_8_3_]], ^bb1([[VAR_3_15_]] : !llvm.ptr), ^bb2
// CHECK: ^bb1([[VAR_9_2_:%.+]]: !llvm.ptr): // 2 preds: ^bb0, ^bb2
// CHECK: ^bb1([[VAR_9_2_:%.+]]: !llvm.ptr): // 3 preds: ^bb0, ^bb2, ^bb2
// CHECK: llvm.return [[VAR_9_2_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_10_3_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_2_15_]], [[VAR_1_15_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_11_3_:%.+]] = llvm.icmp "eq" [[VAR_10_3_]], [[VAR_5_12_]] : i32
// CHECK: llvm.cond_br [[VAR_11_3_]], ^bb1([[VAR_0_13_]] : !llvm.ptr), ^bb3
// CHECK: ^bb3: // pred: ^bb2
// CHECK: [[VAR_12_3_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.return [[VAR_12_3_]] : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_11_3_]], ^bb1([[VAR_0_13_]] : !llvm.ptr), ^bb1([[VAR_0]] : !llvm.ptr)
// CHECK: }

// CHECK: llvm.func @omOutputSignature([[arg0_:%.+]]: !llvm.ptr) -> !llvm.ptr {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[VAR_0_14_:%.+]] = llvm.mlir.addressof @_entry_point_1_out_sig : !llvm.ptr
// CHECK-DAG: [[VAR_1_16_:%.+]] = llvm.mlir.constant(17 : i64) : i64
// CHECK-DAG: [[VAR_2_16_:%.+]] = llvm.mlir.addressof @_entry_point_1 : !llvm.ptr
Expand All @@ -155,15 +150,12 @@ module {
// CHECK: [[VAR_7_4_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_6_10_]], [[VAR_4_11_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_8_4_:%.+]] = llvm.icmp "eq" [[VAR_7_4_]], [[VAR_5_13_]] : i32
// CHECK: llvm.cond_br [[VAR_8_4_]], ^bb1([[VAR_3_16_]] : !llvm.ptr), ^bb2
// CHECK: ^bb1([[VAR_9_2_:%.+]]: !llvm.ptr): // 2 preds: ^bb0, ^bb2
// CHECK: ^bb1([[VAR_9_2_:%.+]]: !llvm.ptr): // 3 preds: ^bb0, ^bb2, ^bb2
// CHECK: llvm.return [[VAR_9_2_]] : !llvm.ptr
// CHECK: ^bb2: // pred: ^bb0
// CHECK: [[VAR_10_4_:%.+]] = llvm.call @strncmp([[arg0_]], [[VAR_2_16_]], [[VAR_1_16_]]) : (!llvm.ptr, !llvm.ptr, i64) -> i32
// CHECK: [[VAR_11_4_:%.+]] = llvm.icmp "eq" [[VAR_10_4_]], [[VAR_5_13_]] : i32
// CHECK: llvm.cond_br [[VAR_11_4_]], ^bb1([[VAR_0_14_]] : !llvm.ptr), ^bb3
// CHECK: ^bb3: // pred: ^bb2
// CHECK: [[VAR_12_4_:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK: llvm.return [[VAR_12_4_]] : !llvm.ptr
// CHECK: llvm.cond_br [[VAR_11_4_]], ^bb1([[VAR_0_14_]] : !llvm.ptr), ^bb1([[VAR_0]] : !llvm.ptr)
// CHECK: }
}

Expand All @@ -178,15 +170,15 @@ module attributes {"onnx-mlir.accels" = ["Pseudo-0x10001", "NNPA-0x10000"]} {
// CHECK: llvm.func @OMInitCompatibleAccelNNPA(i64)
// CHECK: llvm.func @OMInitCompatibleAccelPseudo(i64)
// CHECK: llvm.func @run_main_graph({{.*}}: !llvm.ptr) -> !llvm.ptr {
// CHECK-DAG: [[VAR_0:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-DAG: [[FALSE:%.+]] = llvm.mlir.constant(0 : i64) : i64
// CHECK-DAG: [[VERSION_NUMBER_0:%.+]] = llvm.mlir.constant(65537 : i64) : i64
// CHECK-DAG: [[VERSION_NUMBER_1:%.+]] = llvm.mlir.constant(65536 : i64) : i64
// CHECK: [[COMPATIBLE:%.+]] = llvm.call @OMInitCompatibleAccelPseudo([[VERSION_NUMBER_0]]) : (i64) -> i64
// CHECK-NEXT: [[FAILED:%.+]] = llvm.icmp "eq" [[COMPATIBLE]], [[FALSE]] : i64
// CHECK-NEXT: llvm.cond_br [[FAILED]], ^bb1, ^bb2
// CHECK-NEXT: ^bb1: // 2 preds: ^bb0, ^bb2
// CHECK-NEXT: [[NULL:%.+]] = llvm.mlir.zero : !llvm.ptr
// CHECK-NEXT: llvm.return [[NULL]] : !llvm.ptr
// CHECK-NEXT: llvm.return [[VAR_0]] : !llvm.ptr
// CHECK-NEXT: ^bb2: // pred: ^bb0
// CHECK-NEXT: [[COMPATIBLE:%.+]] = llvm.call @OMInitCompatibleAccelNNPA([[VERSION_NUMBER_1]]) : (i64) -> i64
// CHECK-NEXT: [[FAILED:%.+]] = llvm.icmp "eq" [[COMPATIBLE]], [[FALSE]] : i64
Expand Down
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