Skip to content

Commit a33ad50

Browse files
mmickommicko
committed
Add bram with initialization support
1 parent a11d8fc commit a33ad50

File tree

6 files changed

+280
-227
lines changed

6 files changed

+280
-227
lines changed

‎techlibs/nanoxplore/Makefile.inc

+1
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ OBJS += techlibs/nanoxplore/nx_carry.o
44

55
# Techmap
66
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
7+
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
78
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
89
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
910
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))

‎techlibs/nanoxplore/brams.txt

+33-33
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,39 @@
11
ram block $__NX_RAM_ {
2-
option "STD_MODE" "NOECC_48kx1" {
3-
# only 32k used
4-
abits 15;
5-
widths 1 global;
6-
}
7-
option "STD_MODE" "NOECC_24kx2" {
8-
# only 16k used
9-
abits 14;
10-
widths 2 global;
11-
}
12-
option "STD_MODE" "NOECC_16kx3" {
13-
abits 14;
14-
widths 3 global;
15-
}
16-
option "STD_MODE" "NOECC_12kx4" {
17-
# only 8k used
18-
abits 13;
19-
widths 4 global;
20-
}
21-
option "STD_MODE" "NOECC_8kx6" {
22-
abits 13;
23-
widths 6 global;
24-
}
25-
option "STD_MODE" "NOECC_6kx8" {
26-
# only 4k used
27-
abits 12;
28-
widths 8 global;
29-
}
30-
option "STD_MODE" "NOECC_4kx12" {
31-
abits 12;
32-
widths 12 global;
33-
}
2+
# option "STD_MODE" "NOECC_48kx1" {
3+
# # only 32k used
4+
# abits 15;
5+
# widths 1 per_port;
6+
# }
7+
# option "STD_MODE" "NOECC_24kx2" {
8+
# # only 16k used
9+
# abits 14;
10+
# widths 2 per_port;
11+
# }
12+
# option "STD_MODE" "NOECC_16kx3" {
13+
# abits 14;
14+
# widths 3 per_port;
15+
# }
16+
# option "STD_MODE" "NOECC_12kx4" {
17+
# # only 8k used
18+
# abits 13;
19+
# widths 4 per_port;
20+
# }
21+
# option "STD_MODE" "NOECC_8kx6" {
22+
# abits 13;
23+
# widths 6 per_port;
24+
# }
25+
# option "STD_MODE" "NOECC_6kx8" {
26+
# # only 4k used
27+
# abits 12;
28+
# widths 8 per_port;
29+
# }
30+
# option "STD_MODE" "NOECC_4kx12" {
31+
# abits 12;
32+
# widths 12 per_port;
33+
# }
3434
option "STD_MODE" "NOECC_2kx24" {
3535
abits 11;
36-
widths 24 global;
36+
widths 24 per_port;
3737
}
3838
cost 64;
3939
init no_undef;

‎techlibs/nanoxplore/brams_init.vh

+17
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
function [409600-1:0] bram_init_to_string;
2+
input [49152-1:0] array;
3+
input integer blocks;
4+
input integer width;
5+
reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
6+
integer i;
7+
begin
8+
temp = "";
9+
for (i = 0; i < blocks; i = i + 1) begin
10+
if (i != 0) begin
11+
temp = {temp, ","};
12+
end
13+
temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])};
14+
end
15+
bram_init_to_string = temp;
16+
end
17+
endfunction

‎techlibs/nanoxplore/brams_map.v

+26-22
Original file line numberDiff line numberDiff line change
@@ -3,26 +3,30 @@ module $__NX_RAM_ (...);
33
parameter INIT = 0;
44
parameter OPTION_STD_MODE = "NOECC_24kx2";
55

6-
parameter WIDTH = 24;
6+
parameter PORT_A_WIDTH = 24;
7+
parameter PORT_B_WIDTH = 24;
8+
79
parameter PORT_A_CLK_POL = 1;
810

911
input PORT_A_CLK;
1012
input PORT_A_CLK_EN;
1113
input PORT_A_WR_EN;
1214
input [15:0] PORT_A_ADDR;
13-
input [WIDTH-1:0] PORT_A_WR_DATA;
15+
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
1416
wire [24-1:0] A_DATA;
15-
output [WIDTH-1:0] PORT_A_RD_DATA;
17+
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
1618

1719
parameter PORT_B_CLK_POL = 1;
1820

1921
input PORT_B_CLK;
2022
input PORT_B_CLK_EN;
2123
input PORT_B_WR_EN;
2224
input [15:0] PORT_B_ADDR;
23-
input [WIDTH-1:0] PORT_B_WR_DATA;
25+
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
2426
wire [24-1:0] B_DATA;
25-
output [WIDTH-1:0] PORT_B_RD_DATA;
27+
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
28+
29+
`include "brams_init.vh"
2630

2731
function [15:0] raw_config1_func;
2832
begin
@@ -55,32 +59,32 @@ endfunction
5559

5660
generate
5761
if (OPTION_STD_MODE == "NOECC_48kx1") begin
58-
assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
59-
assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
62+
assign A_DATA = {24{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
63+
assign B_DATA = {24{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
6064
end
6165
else if (OPTION_STD_MODE == "NOECC_24kx2") begin
62-
assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
63-
assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
66+
assign A_DATA = {12{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
67+
assign B_DATA = {12{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
6468
end
6569
else if (OPTION_STD_MODE == "NOECC_16kx3") begin
66-
assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
67-
assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
70+
assign A_DATA = {8{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
71+
assign B_DATA = {8{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
6872
end
6973
else if (OPTION_STD_MODE == "NOECC_12kx4") begin
70-
assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
71-
assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
74+
assign A_DATA = {6{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
75+
assign B_DATA = {6{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
7276
end
7377
else if (OPTION_STD_MODE == "NOECC_8kx6") begin
74-
assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
75-
assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
78+
assign A_DATA = {4{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
79+
assign B_DATA = {4{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
7680
end
7781
else if (OPTION_STD_MODE == "NOECC_6kx8") begin
78-
assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
79-
assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
82+
assign A_DATA = {3{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
83+
assign B_DATA = {3{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
8084
end
8185
else if (OPTION_STD_MODE == "NOECC_4kx12") begin
82-
assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
83-
assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
86+
assign A_DATA = {2{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
87+
assign B_DATA = {2{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
8488
end
8589
else if (OPTION_STD_MODE == "NOECC_2kx24") begin
8690
assign A_DATA = PORT_A_WR_DATA;
@@ -98,7 +102,7 @@ NX_RAM_WRAP #(
98102
.pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
99103
.raw_config0(4'b0000),
100104
.raw_config1(raw_config1_func()),
101-
.mem_ctxt("")
105+
.mem_ctxt($sformatf("%s",bram_init_to_string(INIT, 2048, 24))),
102106
) _TECHMAP_REPLACE_ (
103107
.ACK(PORT_A_CLK),
104108
//.ACKS(PORT_A_CLK),
@@ -123,8 +127,8 @@ NX_RAM_WRAP #(
123127
//.BERR(),
124128
.BCS(PORT_B_CLK_EN),
125129
.BWE(PORT_B_WR_EN),
126-
.BA(B_DATA),
127-
.BI(PORT_B_WR_DATA),
130+
.BA(PORT_B_ADDR),
131+
.BI(B_DATA),
128132
.BO(PORT_B_RD_DATA)
129133
);
130134
endmodule

‎techlibs/nanoxplore/cells_bb.v

-172
Original file line numberDiff line numberDiff line change
@@ -90,178 +90,6 @@ endmodule
9090
// parameter ring = 0;
9191
//endmodule
9292

93-
(* blackbox *)
94-
module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
95-
, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
96-
, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
97-
, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
98-
, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
99-
, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
100-
, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
101-
input AA1;
102-
input AA10;
103-
input AA11;
104-
input AA12;
105-
input AA13;
106-
input AA14;
107-
input AA15;
108-
input AA16;
109-
input AA2;
110-
input AA3;
111-
input AA4;
112-
input AA5;
113-
input AA6;
114-
input AA7;
115-
input AA8;
116-
input AA9;
117-
input ACK;
118-
input ACKC;
119-
input ACKD;
120-
input ACKR;
121-
output ACOR;
122-
input ACS;
123-
output AERR;
124-
input AI1;
125-
input AI10;
126-
input AI11;
127-
input AI12;
128-
input AI13;
129-
input AI14;
130-
input AI15;
131-
input AI16;
132-
input AI17;
133-
input AI18;
134-
input AI19;
135-
input AI2;
136-
input AI20;
137-
input AI21;
138-
input AI22;
139-
input AI23;
140-
input AI24;
141-
input AI3;
142-
input AI4;
143-
input AI5;
144-
input AI6;
145-
input AI7;
146-
input AI8;
147-
input AI9;
148-
output AO1;
149-
output AO10;
150-
output AO11;
151-
output AO12;
152-
output AO13;
153-
output AO14;
154-
output AO15;
155-
output AO16;
156-
output AO17;
157-
output AO18;
158-
output AO19;
159-
output AO2;
160-
output AO20;
161-
output AO21;
162-
output AO22;
163-
output AO23;
164-
output AO24;
165-
output AO3;
166-
output AO4;
167-
output AO5;
168-
output AO6;
169-
output AO7;
170-
output AO8;
171-
output AO9;
172-
input AR;
173-
input AWE;
174-
input BA1;
175-
input BA10;
176-
input BA11;
177-
input BA12;
178-
input BA13;
179-
input BA14;
180-
input BA15;
181-
input BA16;
182-
input BA2;
183-
input BA3;
184-
input BA4;
185-
input BA5;
186-
input BA6;
187-
input BA7;
188-
input BA8;
189-
input BA9;
190-
input BCK;
191-
input BCKC;
192-
input BCKD;
193-
input BCKR;
194-
output BCOR;
195-
input BCS;
196-
output BERR;
197-
input BI1;
198-
input BI10;
199-
input BI11;
200-
input BI12;
201-
input BI13;
202-
input BI14;
203-
input BI15;
204-
input BI16;
205-
input BI17;
206-
input BI18;
207-
input BI19;
208-
input BI2;
209-
input BI20;
210-
input BI21;
211-
input BI22;
212-
input BI23;
213-
input BI24;
214-
input BI3;
215-
input BI4;
216-
input BI5;
217-
input BI6;
218-
input BI7;
219-
input BI8;
220-
input BI9;
221-
output BO1;
222-
output BO10;
223-
output BO11;
224-
output BO12;
225-
output BO13;
226-
output BO14;
227-
output BO15;
228-
output BO16;
229-
output BO17;
230-
output BO18;
231-
output BO19;
232-
output BO2;
233-
output BO20;
234-
output BO21;
235-
output BO22;
236-
output BO23;
237-
output BO24;
238-
output BO3;
239-
output BO4;
240-
output BO5;
241-
output BO6;
242-
output BO7;
243-
output BO8;
244-
output BO9;
245-
input BR;
246-
input BWE;
247-
parameter mcka_edge = 1'b0;
248-
parameter mckb_edge = 1'b0;
249-
parameter mem_ctxt = "";
250-
parameter pcka_edge = 1'b0;
251-
parameter pckb_edge = 1'b0;
252-
parameter pipe_ia = 1'b0;
253-
parameter pipe_ib = 1'b0;
254-
parameter pipe_oa = 1'b0;
255-
parameter pipe_ob = 1'b0;
256-
parameter raw_config0 = 4'b0000;
257-
parameter raw_config1 = 16'b0000000000000000;
258-
//parameter raw_l_enable = 1'b0;
259-
//parameter raw_l_extend = 4'b0000;
260-
//parameter raw_u_enable = 1'b0;
261-
//parameter raw_u_extend = 8'b00000000;
262-
parameter std_mode = "";
263-
endmodule
264-
26593
// NX_RAM related
26694
(* blackbox *)
26795
module NX_ECC(CKD, CHK, COR, ERR);

0 commit comments

Comments
 (0)