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Add bram with initialization support
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@mmicko
mmicko committed May 28, 2024
1 parent a11d8fc commit a33ad50
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Showing 6 changed files with 280 additions and 227 deletions.
1 change: 1 addition & 0 deletions techlibs/nanoxplore/Makefile.inc
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Expand Up @@ -4,6 +4,7 @@ OBJS += techlibs/nanoxplore/nx_carry.o

# Techmap
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
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66 changes: 33 additions & 33 deletions techlibs/nanoxplore/brams.txt
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@@ -1,39 +1,39 @@
ram block $__NX_RAM_ {
option "STD_MODE" "NOECC_48kx1" {
# only 32k used
abits 15;
widths 1 global;
}
option "STD_MODE" "NOECC_24kx2" {
# only 16k used
abits 14;
widths 2 global;
}
option "STD_MODE" "NOECC_16kx3" {
abits 14;
widths 3 global;
}
option "STD_MODE" "NOECC_12kx4" {
# only 8k used
abits 13;
widths 4 global;
}
option "STD_MODE" "NOECC_8kx6" {
abits 13;
widths 6 global;
}
option "STD_MODE" "NOECC_6kx8" {
# only 4k used
abits 12;
widths 8 global;
}
option "STD_MODE" "NOECC_4kx12" {
abits 12;
widths 12 global;
}
# option "STD_MODE" "NOECC_48kx1" {
# # only 32k used
# abits 15;
# widths 1 per_port;
# }
# option "STD_MODE" "NOECC_24kx2" {
# # only 16k used
# abits 14;
# widths 2 per_port;
# }
# option "STD_MODE" "NOECC_16kx3" {
# abits 14;
# widths 3 per_port;
# }
# option "STD_MODE" "NOECC_12kx4" {
# # only 8k used
# abits 13;
# widths 4 per_port;
# }
# option "STD_MODE" "NOECC_8kx6" {
# abits 13;
# widths 6 per_port;
# }
# option "STD_MODE" "NOECC_6kx8" {
# # only 4k used
# abits 12;
# widths 8 per_port;
# }
# option "STD_MODE" "NOECC_4kx12" {
# abits 12;
# widths 12 per_port;
# }
option "STD_MODE" "NOECC_2kx24" {
abits 11;
widths 24 global;
widths 24 per_port;
}
cost 64;
init no_undef;
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17 changes: 17 additions & 0 deletions techlibs/nanoxplore/brams_init.vh
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@@ -0,0 +1,17 @@
function [409600-1:0] bram_init_to_string;
input [49152-1:0] array;
input integer blocks;
input integer width;
reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
integer i;
begin
temp = "";
for (i = 0; i < blocks; i = i + 1) begin
if (i != 0) begin
temp = {temp, ","};
end
temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])};
end
bram_init_to_string = temp;
end
endfunction
48 changes: 26 additions & 22 deletions techlibs/nanoxplore/brams_map.v
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Expand Up @@ -3,26 +3,30 @@ module $__NX_RAM_ (...);
parameter INIT = 0;
parameter OPTION_STD_MODE = "NOECC_24kx2";

parameter WIDTH = 24;
parameter PORT_A_WIDTH = 24;
parameter PORT_B_WIDTH = 24;

parameter PORT_A_CLK_POL = 1;

input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input [15:0] PORT_A_ADDR;
input [WIDTH-1:0] PORT_A_WR_DATA;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
wire [24-1:0] A_DATA;
output [WIDTH-1:0] PORT_A_RD_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;

parameter PORT_B_CLK_POL = 1;

input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input [15:0] PORT_B_ADDR;
input [WIDTH-1:0] PORT_B_WR_DATA;
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
wire [24-1:0] B_DATA;
output [WIDTH-1:0] PORT_B_RD_DATA;
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;

`include "brams_init.vh"

function [15:0] raw_config1_func;
begin
Expand Down Expand Up @@ -55,32 +59,32 @@ endfunction

generate
if (OPTION_STD_MODE == "NOECC_48kx1") begin
assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {24{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {24{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_24kx2") begin
assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {12{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {12{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_16kx3") begin
assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {8{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {8{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_12kx4") begin
assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {6{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {6{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_8kx6") begin
assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {4{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {4{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_6kx8") begin
assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {3{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {3{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_4kx12") begin
assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
assign A_DATA = {2{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
assign B_DATA = {2{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_2kx24") begin
assign A_DATA = PORT_A_WR_DATA;
Expand All @@ -98,7 +102,7 @@ NX_RAM_WRAP #(
.pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
.raw_config0(4'b0000),
.raw_config1(raw_config1_func()),
.mem_ctxt("")
.mem_ctxt($sformatf("%s",bram_init_to_string(INIT, 2048, 24))),
) _TECHMAP_REPLACE_ (
.ACK(PORT_A_CLK),
//.ACKS(PORT_A_CLK),
Expand All @@ -123,8 +127,8 @@ NX_RAM_WRAP #(
//.BERR(),
.BCS(PORT_B_CLK_EN),
.BWE(PORT_B_WR_EN),
.BA(B_DATA),
.BI(PORT_B_WR_DATA),
.BA(PORT_B_ADDR),
.BI(B_DATA),
.BO(PORT_B_RD_DATA)
);
endmodule
172 changes: 0 additions & 172 deletions techlibs/nanoxplore/cells_bb.v
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Expand Up @@ -90,178 +90,6 @@ endmodule
// parameter ring = 0;
//endmodule

(* blackbox *)
module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
input AA1;
input AA10;
input AA11;
input AA12;
input AA13;
input AA14;
input AA15;
input AA16;
input AA2;
input AA3;
input AA4;
input AA5;
input AA6;
input AA7;
input AA8;
input AA9;
input ACK;
input ACKC;
input ACKD;
input ACKR;
output ACOR;
input ACS;
output AERR;
input AI1;
input AI10;
input AI11;
input AI12;
input AI13;
input AI14;
input AI15;
input AI16;
input AI17;
input AI18;
input AI19;
input AI2;
input AI20;
input AI21;
input AI22;
input AI23;
input AI24;
input AI3;
input AI4;
input AI5;
input AI6;
input AI7;
input AI8;
input AI9;
output AO1;
output AO10;
output AO11;
output AO12;
output AO13;
output AO14;
output AO15;
output AO16;
output AO17;
output AO18;
output AO19;
output AO2;
output AO20;
output AO21;
output AO22;
output AO23;
output AO24;
output AO3;
output AO4;
output AO5;
output AO6;
output AO7;
output AO8;
output AO9;
input AR;
input AWE;
input BA1;
input BA10;
input BA11;
input BA12;
input BA13;
input BA14;
input BA15;
input BA16;
input BA2;
input BA3;
input BA4;
input BA5;
input BA6;
input BA7;
input BA8;
input BA9;
input BCK;
input BCKC;
input BCKD;
input BCKR;
output BCOR;
input BCS;
output BERR;
input BI1;
input BI10;
input BI11;
input BI12;
input BI13;
input BI14;
input BI15;
input BI16;
input BI17;
input BI18;
input BI19;
input BI2;
input BI20;
input BI21;
input BI22;
input BI23;
input BI24;
input BI3;
input BI4;
input BI5;
input BI6;
input BI7;
input BI8;
input BI9;
output BO1;
output BO10;
output BO11;
output BO12;
output BO13;
output BO14;
output BO15;
output BO16;
output BO17;
output BO18;
output BO19;
output BO2;
output BO20;
output BO21;
output BO22;
output BO23;
output BO24;
output BO3;
output BO4;
output BO5;
output BO6;
output BO7;
output BO8;
output BO9;
input BR;
input BWE;
parameter mcka_edge = 1'b0;
parameter mckb_edge = 1'b0;
parameter mem_ctxt = "";
parameter pcka_edge = 1'b0;
parameter pckb_edge = 1'b0;
parameter pipe_ia = 1'b0;
parameter pipe_ib = 1'b0;
parameter pipe_oa = 1'b0;
parameter pipe_ob = 1'b0;
parameter raw_config0 = 4'b0000;
parameter raw_config1 = 16'b0000000000000000;
//parameter raw_l_enable = 1'b0;
//parameter raw_l_extend = 4'b0000;
//parameter raw_u_enable = 1'b0;
//parameter raw_u_extend = 8'b00000000;
parameter std_mode = "";
endmodule

// NX_RAM related
(* blackbox *)
module NX_ECC(CKD, CHK, COR, ERR);
Expand Down
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