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hierarchy: Without a known top module, derive all deferred modules
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This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
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jix committed Feb 5, 2024
1 parent 2422dd6 commit b500e16
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Showing 2 changed files with 13 additions and 1 deletion.
12 changes: 12 additions & 0 deletions passes/hierarchy/hierarchy.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1006,6 +1006,18 @@ struct HierarchyPass : public Pass {
if (mod->get_bool_attribute(ID::top))
top_mod = mod;

if (top_mod == nullptr)
{
std::vector<IdString> abstract_ids;
for (auto module : design->modules())
if (module->name.begins_with("$abstract"))
abstract_ids.push_back(module->name);
for (auto abstract_id : abstract_ids)
design->module(abstract_id)->derive(design, {});
for (auto abstract_id : abstract_ids)
design->remove(design->module(abstract_id));
}

if (top_mod == nullptr && auto_top_mode) {
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;
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2 changes: 1 addition & 1 deletion tests/verilog/param_no_default.ys
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
read_verilog -sv param_no_default.sv
hierarchy
hierarchy -top top
proc
flatten
opt -full
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