rtlil: Add wire deletion test

povik · povik · commit fb55e3f88ad4 · 2024-01-22T14:42:45.000+01:00
diff --git a/tests/various/bug4082.ys b/tests/various/bug4082.ys
@@ -0,0 +1,8 @@
+read_verilog <<EOF
+module top;
+  wire a;
+  wire b;
+  assign a = b;
+endmodule
+EOF
+delete w:a
