Mapping to more compex gate types

[cpldcpu]

I am currently trying to use Yosys to synthesize VHDL to single gate logic. (It's more of a learning project).

I have used the CMOS example as a starting point and changed the liberty file. One of the gates I am trying to map to is a univerial logic device. The description is:

cell(SZ57) {
    area: 1;
    pin(A) { direction: input; }
    pin(B) { direction: input; }
    pin(C) { direction: input; }
    pin(Y) { direction: output;
             function: "((A'*C')+(B*C))"; }
  }

In principle, any arbitrary logic function can be formed by this gate. Unfortunately this cell is only used in places where it is preexisting, so it is rarely used in my test design.

Is there any way of using ABC or the rest of the toolchain to transform single gate logic into this more complex one?