Using register retiming with yosys

[chidori430]

Hi, I'm fairly new to yosys but I wanted to synthesis a small verilog design with retiming and I am unsure of how to do so. I saw some documentation using abc with the -dff -D 1 flags but I wasn't sure if this was the correct way to do so. Also, is there anyway to tell what performance gains I would get from register retiming?

[Ravenslofty]

Are you synthesising for ASIC or FPGA? abc -dff -D 1 won't retime for FPGA.

[chidori430]

This was for an ASIC. The -v didn't give me any extra output so I wasn't sure what was happening.

[Ravenslofty]

I assume you're using a Liberty library then, right? If so, are you calling dfflibmap before abc? That would inhibit retiming, as I understand it.

[chidori430]

Oh, I see. I didn't know that dfflibmap would inhibit it. How does that command inhibit retiming? I didn't see anything in the documentation about that.

[Ravenslofty]

ABC's retiming operations work on BLIF's native DFF model, and to output those with -dff you need native Yosys flop cells ($_DFF_XXX_ and friends). If you map before retiming Yosys doesn't know how to express them in BLIF for ABC to load, so they get hidden, and no retiming can be performed.

[chidori430]

Ahh, that makes sense. That just solved the issue I was having. Thank you so much!

[Vinayakamk]

@chidori430 @Ravenslofty pleasure to chat with u.im very new to this yosys..
can u guys help me out how to do retiming(re arranging registers) ,in step by step manner
that could be of more help
thank you

[nakengelhardt]

@Vinayakamk please stop spamming unrelated issues/questions/PRs. We have seen your question.

[Vinayakamk]

You could have kindly answered my question... I asked sincerely that I'm new to it.and I have tried too..I got it ,but not sure about the answer.

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