Critical-Path Optimization

[alexander-c-b]

Dear Yosys community,

I am fairly new to RTL synthesis and the FOSS tools that support it. Is there a way to use optimize the critical path of a Verilog circuit using Yosys, or any related synthesis tools?

Thanks!
Alexander C. Bodoh

[nakengelhardt]

Yosys doesn't currently have any timing-aware optimizations. The closest related thing is ABC's delay target, you could experiment with setting the -D argument of abc (if you're running one of the synth_* passes, you can run scratchpad -set abc.D x beforehand).

[alexander-c-b]

Thank you for the advice! I was able to get critical-path optimization working very well using ABC as a standalone tool. Best regards, Alexander C. Bodoh Edit: Below is a reply to @krangerich, which I've included here since it serves as an answer to the question originally posted. It took me a while to find how in the documentation, but critical-path optimization, or equivalently (in my case) reduction of gate levels, is apparently simple in ABC. Note that I use `yosys-abc` as the executable since it is provided with `yosys`, but it should be mostly identical to the upstream version of `abc`. The main commands are as follows: `read_library` must be used to tell ABC what gate technology you'll use for the combinational network; it uses the genlib format, an example of which I have posted at the bottom of this comment. `read_verilog` inputs the Verilog netlist into ABC; the `-m` flag tells ABC that it uses the mapping defined in the library you provided. `strash` converts the Verilog netlist into ABC's internal AND-inverter-graph representation which is used for optimization. `resyn` is a script which does the actual optimization, defined in `abc.rc`, which may be found somewhere in `yosys`'s installation directory. `map` maps the AND-inverter-graph back into your target technology (which can be different from your original technology if you use `read_library` again after running `resyn`). Finally, `write_verilog` writes the optimized Verilog netlist to a given file. Below is a script similar to what I used: ``` read_library lib.genlib; read_verilog -m in.v; strash; resyn; map; write_verilog out.v; ``` Example `lib.genlib`: ``` GATE zero 1 y=CONST0; GATE one 1 y=CONST1; GATE not1 1 y=!a; PIN * INV 1 999 1 0 1 0 GATE buf1 1 y=a; PIN * NONINV 1 999 1 0 1 0 GATE nor2 1 y=!(a+b); PIN * INV 1 999 1 0 1 0 GATE nor3 1 y=!(a+b+c); PIN * INV 1 999 1 0 1 0 GATE nor4 1 y=!(a+b+c+d); PIN * INV 1 999 1 0 1 0 GATE nand2 1 y=!(a*b); PIN * INV 1 999 1 0 1 0 GATE nand3 1 y=!(a*b*c); PIN * INV 1 999 1 0 1 0 GATE nand4 1 y=!(a*b*c*d); PIN * INV 1 999 1 0 1 0 GATE or2 1 y=a+b; PIN * NONINV 1 999 1 0 1 0 GATE or3 1 y=a+b+c; PIN * NONINV 1 999 1 0 1 0 GATE or4 1 y=a+b+c+d; PIN * NONINV 1 999 1 0 1 0 GATE and2 1 y=a*b; PIN * NONINV 1 999 1 0 1 0 GATE and3 1 y=a*b*c; PIN * NONINV 1 999 1 0 1 0 GATE and4 1 y=a*b*c*d; PIN * NONINV 1 999 1 0 1 0 GATE xor2 1 y=(a*!b)+(!a*b); PIN * UNKNOWN 1 999 1 0 1 0 GATE xnor2 1 y=(a*b)+(!a*!b); PIN * UNKNOWN 1 999 1 0 1 0 ```

[krangerich]

How did you achieve that? I consider myself a beginner and I see the existing abc "documentation" aimed towards expert abc contributors, but not useful for people not familiar with abc.

[alexander-c-b]

Hello @krangerich,

I have edited my original answer in response to your question, since the response also serves as an answer to the original discussion question. Please let me know if there is anything else you'd like to ask.

Best regards,
Alexander C. Bodoh

[krangerich]

Nice! That is very helpful in order to get started with abc, thank you very much