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I need to make all DFFs in a foreign design accessible from the outside.
My current approach is to export a synthesized netlist as json and manipulate it via python and finally to import it again.
The manipulation consist of essentially a techmap in which I replace all DFFs with a scan chain enabled instance and the propagation of the additional ports up to the toplevel.
I.e. if I have a design with 10 DFFs, I get 3 additional vector ports with length 10 in the toplevel connected to each DFF input, output and "scan chain enable" flag.
Finally the toplevel is wrapped and the individual input,output and enable of each scan chain enabled DFF are connected to construct the actual chains.
I would like to do this within yosys instead of outside via an external script.
The mapping/techmap port can be obviously solved with techmap, but I see no way of propagating ports from a submodule to the toplevel.
The expose pass seems to only act on wires and gives no naming control.
Did I overlook sth? If not, should I introduce the propagate_port pass?
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I need to make all DFFs in a foreign design accessible from the outside.
My current approach is to export a synthesized netlist as json and manipulate it via python and finally to import it again.
The manipulation consist of essentially a techmap in which I replace all DFFs with a scan chain enabled instance and the propagation of the additional ports up to the toplevel.
I.e. if I have a design with 10 DFFs, I get 3 additional vector ports with length 10 in the toplevel connected to each DFF input, output and "scan chain enable" flag.
Finally the toplevel is wrapped and the individual input,output and enable of each scan chain enabled DFF are connected to construct the actual chains.
I would like to do this within yosys instead of outside via an external script.
The mapping/techmap port can be obviously solved with techmap, but I see no way of propagating ports from a submodule to the toplevel.
The
expose
pass seems to only act on wires and gives no naming control.Did I overlook sth? If not, should I introduce the
propagate_port
pass?Beta Was this translation helpful? Give feedback.
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