How to map the circuit into LUT and DFF in yosys？

[ghost]

There is no asynchronous reset port and latch in my circuit, so I want to map it into LUT and DFF only. Now, I find a minimum lib (with INV BUF NAND2 DFF), and my circuit can map to this lib successfully, but I do not know how to further map the INV, BUF, NAND2 into LUT, and therefore I can get a circuit with LUT and DFF only？

[nakengelhardt]

You can use e.g. synth -lut 4 to map the combinatorial logic to 4-LUT. If you only want strictly $_DFF_[PN]_ (no enable or reset signal on DFF cells) you can use the following script:

synth -noabc -top <top_module>
dfflegalize -cell $_DFF_?_ 01
abc -lut 4
opt

This should leave you with only $lut and $_DFF_P_/$_DFF_N_ cells in the circuit.

[ghost]

Thank you very much!

[Maerd6]

Hi. I have another quetions about convert xilinx lut structure to logic gates like and, or. Can I manage it using yosys? Can you give me some suggestions?

[ghost]

Hi, I think if you can acquire the LUT connection of a circuit, it is easy to convert it to the basic logic gate, for example, the lut4 and it's confgiuration information (16bit) can stand for a truth table, based on the truth table, it is easy to convert it to basic logic gates, but I do not know how to deal this problem in yosys.

[Maerd6]

Thank you very much!

[GPJ-ZFF]

Hi，I am currently seeking to validate the consistency of the netlist pre and post technology mapping. I believe there is potential to expand the LUT in order to achieve the basic and-OR gate logic function. What would be the next steps? Are there any relevant literature recommendations?