SB_IO_I3C needed in iCE40UP5K

[XYZLassi]

Hello together,

I need the SB_IO_I3C of the iCE40UP for an application. Unfortunately, I get that the cell type is not supported.

ERROR: cell type 'SB_IO_I3C' is unsupported (instantiated as 'pdm1_i3c.i3c_primitive')

I hope you can help me how to get the IO blocks.

Here is the code:

makefile:

yosys -m ghdl -p 'ghdl --workdir=work -P=lib main.vhd i3c.vhd -e main; synth_ice40 -json $@'
nextpnr-ice40 --up5k --package sg48 --pcf main.pcf --json $< --asc $@

main.vhd:

use ieee.std_logic_1164.all;

use work.pkg_common.all;
library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

entity main is
    port (
        cs1to4 : inout std_logic; -- i3c
        clk_ref : in std_logic;
    );
end main;

architecture arch of main is
    signal cs : std_logic := '1';
begin
    PDM1_I3C : entity work.i3c
    generic map (
        OUTPUT_PAD => true
    )
    port map (
       pad => cs1to4,
        logic_in => cs,
        logic_out => open
    );
end arch;

i3c.vhd:

library ieee;
use ieee.std_logic_1164.all;

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

use work.pkg_common.all;

entity i3c is
    generic (
        OUTPUT_PAD : boolean := false -- false for input pad, true for output pad
    );
    port (
        pad : inout std_logic;
        logic_in : in std_logic; -- when pad is an output
        logic_out : out std_logic -- when pad is an input
    );
end i3c;

architecture arch of i3c is

    attribute PULLUP_RESISTOR : string;
    attribute PULLUP_RESISTOR of I3C_PRIMITIVE : label is "10K";

begin

    I3C_PRIMITIVE : SB_IO_I3C
    generic map (
        PIN_TYPE => pin_type(OUTPUT_PAD),
        PULLUP => '1',
        WEAK_PULLUP => '0',
        NEG_TRIGGER => '0',
        IO_STANDARD => "SB_LVCMOS"
    )
    port map (
        PACKAGE_PIN => pad,
        LATCH_INPUT_VALUE => '0',
        CLOCK_ENABLE => '0',
        INPUT_CLK => '0',
        OUTPUT_CLK => '0',
        OUTPUT_ENABLE => '0',
        D_OUT_1 => '0',
        D_OUT_0 => logic_in,
        PU_ENB => '1',
        WEAK_PU_ENB => '0',
        D_IN_1 => open,
        D_IN_0 => logic_out
    );

end arch;