Incorrect netlist generation for the adder of two two-bit numbers

[sdaexpert]

Hi,
I am trying to synthesize the following RTL :

//**********************************************************
_module pseudo_adder_2 (
   input S_1,
   input S_0,
   input V_1,
   input V_0,
   output wire [2:0] out
);
//Note that MSBs  of the both two-bit operands are duplicated  making those 3 bit operands
assign out [2:0] = {S_1, S_1, V_1} + {S_0, S_0, V_0};
endmodule_
//**********************************************************

I use the following TCL file

_read_verilog -sv pseudo_adder_2.v
synth -top pseudo_adder_2
extract_fa
techmap -map cells_adders_for_pseudo_adder_2.v
techmap
opt -fast purge
dfflibmap -liberty ./NangateOpenCellLibrary_typical.lib
abc -liberty ./NangateOpenCellLibrary_typical.lib
clean
write_verilog pseudo_adder_2_netlist.v_ 

Here is the cells_adders_for_pseudo_adder_2.v file I use:

**(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;
 
parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;
 
genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HA_X1 halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CO(X[i]), .S(Y[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HA_X1 halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CO(X[i]), .S(Y[i])
);
end
else begin
HA_X1 halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CO(X[i]), .S(Y[i])
);
end
end
end
else begin
FA_X1 fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CO(X[i]), .S(Y[i])
);
end
end endgenerate
endmodule**  

In the netlist output I see that out[0] is generated correctly, but out[1] is incorrect b/c it has extra inverted. See
the snippet below

 INV_X1 _14_ (
.A(S_0),
.ZN(_04_)
);
INV_X1 _15_ (
.A(S_1),
.ZN(_03_)
);
**INV_X1 _16_ (
.A(_02_),
.ZN(out[1])
);**
INV_X1 _17_ (
.A(_06_),
.ZN(out[2])
);
BUF_X1 _18_ (
.A(_13_),
.Z(_00_)
);
BUF_X1 _19_ (
.A(_13_),
.Z(_05_)
);
BUF_X1 _20_ (
.A(_13_),
.Z(_10_)
);
(* module_not_derived = 32'd1 *)
(* src = "cells_adders_for_pseudo_adder_2.v:83.15-87.12" *)
FA_X1 _21_ (
.A(S_1),
.B(S_0),
.CI(_00_),
.CO(_01_),
**.S(_02_)**
);
(* module_not_derived = 32'd1 *)
(* src = "cells_adders_for_pseudo_adder_2.v:83.15-87.12" *)
FA_X1 _22_ (
.A(_03_),
.B(_04_),
.CI(_05_),
.CO(_06_),
.S(_07_)
);
(* module_not_derived = 32'd1 *)
(* src = "cells_adders_for_pseudo_adder_2.v:36.17-44.14" *)
HA_X1 _23_ (
.A(S_1),
.B(S_0),
.CO(_08_),
.S(_09_)
);
(* module_not_derived = 32'd1 *)
(* src = "cells_adders_for_pseudo_adder_2.v:36.17-44.14" *)
HA_X1 _24_ (
.A(_09_),
.B(_10_),
.CO(_11_),
.S(_12_)
);
(* module_not_derived = 32'd1 *)
(* src = "cells_adders_for_pseudo_adder_2.v:36.17-44.14" *)
HA_X1 _25_ (
.A(V_1),
.B(V_0),
.CO(_13_),
.S(**out[0]**)
);

Looking for the advixe on what could be the reason for the incorrect netlist generation:

Thanks