Worse mapping/optimization with abc(?) in current master

[nils1603]

Hey everyone,

we are trying to resynthesize LUTs into basic gates. We created our own genlib, with the gate types we are looking for.

I noticed significant differences in the result output from the current master of yosys compared to yosys 0.30 and 0.27.
Here is the LUT we are trying to decompose:

module top (I5, I1, I2, I4, I3, I0, O);
input I5;
input I1;
input I2;
input I4;
input I3;
input I0;
output O;

assign O = ((I5 & ((I3 | ((I0 & (! I4)) | ((! I0) & I4))) & ((! I3) | ((I0 | (! I4)) & ((! I0) | I4))))) | ((I3 | ((I0 & (! I2)) | ((! I0) & I2))) & ((! I5) & ((I1 & I4) | ((! I3) | ((! I1) & (! I4)))))));

endmodule

#basic_hal_i4
GATE HAL_VDD 0.0000 O=CONST1;
GATE HAL_GND 0.0000 O=CONST0;
GATE HAL_XOR3 3.0000 O=((A * ((B * C) + ((! B) * (! C)))) + ((! A) * ((B + C) * ((! B) + (! C)))));
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
PIN C NONINV 1 999 1 0 1 0
GATE HAL_MUX3 1.5000 O=((A + (! S1)) * ((C * (! S2)) + (S1 + (B * S2))));
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
PIN C NONINV 1 999 1 0 1 0
PIN S1 NONINV 1 999 1 0 1 0
PIN S2 NONINV 1 999 1 0 1 0
GATE HAL_BUF 1.0000 O=A;
PIN A NONINV 1 999 1 0 1 0
GATE HAL_XOR4 4.0000 O=((B * ((A + ((C * D) + ((! C) * (! D)))) * ((! A) + ((C + D) * ((! C) + (! D)))))) + ((! B) * ((A * ((C * D) + ((! C) * (! D)))) + ((! A) * ((C + D) * ((! C) + (! D)))))));
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
PIN C NONINV 1 999 1 0 1 0
PIN D NONINV 1 999 1 0 1 0
GATE HAL_MUX4 1.5000 O=(((D * (! S2)) + (S1 + (C * S2))) * ((B * (! S2)) + ((! S1) + (A * S2))));
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
PIN C NONINV 1 999 1 0 1 0
PIN D NONINV 1 999 1 0 1 0
PIN S1 NONINV 1 999 1 0 1 0
PIN S2 NONINV 1 999 1 0 1 0
GATE HAL_MUX 1.5000 O=((B + S) * (A + (! S)));
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
PIN S NONINV 1 999 1 0 1 0
GATE HAL_XOR2 2.0000 O=((A + B) * ((! A) + (! B)));
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
GATE HAL_OR2 2.0000 O=(A + B);
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
GATE HAL_AND2 2.0000 O=(A * B);
PIN A NONINV 1 999 1 0 1 0
PIN B NONINV 1 999 1 0 1 0
GATE HAL_INV 1.0000 O=(! A);
PIN A INV 1 999 1 0 1 0

With yosys 0.30/0.27 this is the final output:

7.1.2. Re-integrating ABC results.
ABC RESULTS:           HAL_INV cells:        1
ABC RESULTS:          HAL_XOR2 cells:        2
ABC RESULTS:          HAL_XOR3 cells:        1
ABC RESULTS:          HAL_MUX3 cells:        1
ABC RESULTS:        internal signals:       11
ABC RESULTS:           input signals:        6
ABC RESULTS:          output signals:        1
Removing temp directory.

However, with the current master (where abc has been updated), the output is significant worse:

7.1.2. Re-integrating ABC results.
ABC RESULTS:           HAL_MUX cells:        1
ABC RESULTS:          HAL_XOR2 cells:        3
ABC RESULTS:           HAL_INV cells:        3
ABC RESULTS:          HAL_AND2 cells:        4
ABC RESULTS:           HAL_OR2 cells:        2
ABC RESULTS:        internal signals:       11
ABC RESULTS:           input signals:        6
ABC RESULTS:          output signals:        1
Removing temp directory.

ABC maps the LUT to 13 cells vs. 5. The 5 cells are much "cheaper" area wise.

I attached the logs for synthesis, and my synthesis script. Any ideas what changed? Is this abcs fault or did commands change somewhere in the new version?

Thanks!

# read design
read -sv test.v
hierarchy -top top

# the high-level stuff
synth -top top;

# mapping to internal cell library
techmap; opt

# mapping logic to NangateOpenCellLibrary_functional.lib
abc -genlib new_gate_library.genlib

write_verilog test_opt.v

# cleanup
clean

log_030.txt
log_027.txt
log_master.txt

[nakengelhardt]

We did notice this also and had to adjust a few of our testcases after updating abc in #3796. No idea what changed in abc to make the results worse...

[nils1603]

Interesting. Did you reach out to the abc devs?

[nakengelhardt]

I briefly mentioned it to @benlcb to check if it was a known issue, but he couldn't think of any. Since we didn't keep up with abc updates for a long time before that PR, we'd first have to do a git bisect to see on which abc revision things actually changed, and have an initial look to see if it might be an interaction with something about the way the abc pass gives things to abc... haven't had the time yet.