Removing redundant wire-wire assignments.

[asraa]

Hi all,

I have a model that I've generated that contains many wire-wire assignments that could be removed, but I'm having trouble using Yosys to remove them. The model was hierarchical with many submodules, and then I ran the following script with the following module:

https://gist.github.com/asraa/232196c4ac9be8a39cdf78cc229d64d6

read_verilog test.v
hierarchy -check -top main
techmap; opt
abc -lut 3 -fast
opt_clean -purge
techmap -map map_lut_to_lutmux3.v
flatten
opt_clean -purge
clean

The result of stat after this:

yosys> stat

@t=3690s: 33. Printing statistics.

=== main ===

   Number of wires:             16991970
   Number of wire bits:         18520204
   Number of public wires:       75510
   Number of public wire bits:  1603744
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:             17371340
     lut3                       17371340

As a result, I see many outputs and inputs to the submodules that are not removed, likely because private wire bits were used to flatten the submodule.

  assign v9996 = \v9996_call._out_ ;

I think that I need to expose the private wires as public, and then either run opt -clean, freduce, or something else that will allow Yosys to optimize these assignments. However, running expose isn't quite right, since it seem to create module ports, rather than convert.

[asraa]

Although I'm not sure it's necessary, what seemed to work was running opt; opt_expr; opt; opt_clean -purge after flatten.