What Verilog syntax is supported or what am I doing wrong?

[SergiiDmytruk]

Hi.

I'm trying yosys for an existing project and received suspicious errors related to parsing of event declaration and repeat statement, so I opened Verilog 2005 specification and found this example which includes both of those things (in case my interpretation of production rules was wrong):

module dump;
    event do_dump;

    initial $dumpfile("verilog.dump");
    initial @do_dump
        $dumpvars; //dump variables in the design

    always @do_dump //to begin the dump at event do_dump
    begin
        $dumpon; //no effect the first time through
        repeat (500) @(posedge clock); //dump for 500 cycles
        $dumpoff; //stop the dump
    end

    initial @(do_dump)
        forever #10000 $dumpall; //checkpoint all variables
endmodule

Trying it out:

$ yosys -p 'read_verilog dump.v'
# <skipped the banner>

 Yosys 0.19+2 (git sha1 0098b32c6, x86_64-conda-linux-gnu-cc 11.2.0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1657150340335/work=/usr/local/src/conda/yosys-0.19_10_g0098b32c6 -fdebug-prefix-map=/home/emdeb/data/f4pga/eos-s3/conda/envs/eos-s3=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)


-- Running command `read_verilog dump.v' --

1. Executing Verilog-2005 frontend: dump.v
Parsing Verilog input from `dump.v' to AST representation.
dump.v:2: ERROR: syntax error, unexpected ';', expecting '(' or '['

I understand that 0.19 is a bit old, but latest Verilog lexer doesn't mention event keyword at all. The binary comes from f4pga environment.

These trivial parsing issues puzzle me, similar issues people have when feeding SystemVerilog, but I don't think that's the case here and -sv option makes no difference. Is there something crucial that I'm missing? And yes, I'm not usually dealing with Verilog.

[whitequark]

Events are not synthesizable; no synthesis toolchain I know of will accept them.

[SergiiDmytruk]

Thanks, I thought that file was compiled by https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain, but it wasn't.

Maybe the same is true for repeat (500) @(posedge clock);, which doesn't compile as well. In both of these cases, it would be nice to parse and then explicitly reject them as unsupported, but maybe there are other ways to know these constructs aren't supposed to work.

[whitequark]

There is no general way to know which Verilog constructs are synthesizable or not. This is one of the many irreparable flaws of the text and the process behind IEEE 1800.