How to get the Yosys optimization to work

[yacobUW]

I am trying to get my code to perform basic optimization. I have created a redundent_or Verilog file and it was able to compile but for some reason I cannot see my code get optimized. I am running the opt command, but this doesn't seem to do what I am looking for. Here is the Verilog file I am trying to optimize. I suspect that I am calling the wrong opt command. I would appreciate any insight.

module redundant_or_logic(input A, input B, output Y);
wire intermediate1, intermediate2, intermediate3;

// Redundant OR gates
assign intermediate1 = A | B;
assign intermediate2 = intermediate1 | A;
assign intermediate3 = intermediate2 | B;

// Output
assign Y = intermediate3;
endmodule

And here is the yosys output

/* Generated by Yosys 0.34+23 (git sha1 59fbee4, clang 10.0.0-4ubuntu1 -fPIC -Os) */

(* top = 1 )
( src = "Verilog/redundant_or_logic.v:1.1-11.10" )
module redundant_or_logic(A, B, Y);
( src = "Verilog/redundant_or_logic.v:1.33-1.34" )
input A;
wire A;
( src = "Verilog/redundant_or_logic.v:1.42-1.43" )
input B;
wire B;
( src = "Verilog/redundant_or_logic.v:1.52-1.53" )
output Y;
wire Y;
( src = "Verilog/redundant_or_logic.v:2.8-2.21" )
wire intermediate1;
( src = "Verilog/redundant_or_logic.v:2.23-2.36" )
wire intermediate2;
( src = "Verilog/redundant_or_logic.v:2.38-2.51" )
wire intermediate3;
assign intermediate1 = A |( src = "Verilog/redundant_or_logic.v:5.26-5.31" ) B;
assign intermediate2 = intermediate1 |( src = "Verilog/redundant_or_logic.v:6.26-6.43" ) A;
assign Y = intermediate2 |( src = "Verilog/redundant_or_logic.v:7.26-7.43" *) B;
assign intermediate3 = Y;
endmodule

[nakengelhardt]

What is the full script you are running? I expect the problem is with the other commands in the flow.

[yacobUW]

The script I used is:

read_verilog redundant_or_logic.v

proc; opt; fsm; opt; memory; opt

techmap; opt

write_verilog synth.v