How to properly report the number of sequential cells

[gkamendje]

While printing statistics, I do see that Yosys printouts the following

[00026.471341]    Number of wires:               2278
[00026.471343]    Number of wire bits:           2323
[00026.471345]    Number of public wires:         320
[00026.471347]    Number of public wire bits:     365
[00026.471349]    Number of memories:               0
[00026.471351]    Number of memory bits:            0
[00026.471352]    Number of processes:              0
[00026.471354]    Number of cells:               2316

along with the list of leaf cells (seq and comb) instantiated in the design.
Is there a way to get a count of the number of sequential cells instantiated in the design? What is the difference between a wire and a wire bit?

[povik]

Is there a way to get a count of the number of sequential cells instantiated in the design?

Not that I know of. Adding a way to select sequential cells with the selection syntax (see help select to find out what that is) is something that was brought up today as a sidenote in #4122. If selection syntax had this support it would let you write a command to count sequential cells.

What is the difference between a wire and a wire bit?

Wires can be multibit. Say you have

    wire [7:0] blah;

in Verilog. That counts as a single wire but as 8 wire bits.

[gkamendje]

@povik thanks for clarifying.

[nakengelhardt]

Note that the proposed selector would be only for internal yosys cells. If your design is already mapped to target architecture primitives, they are all considered blackboxes, there is no mechanism for yosys to know what kind of cell it is.

[nakengelhardt]

Also, you can already write a command to count them, it is just a bit more cumbersome without the selector. The equivalent command would be:
select -count t:$sr t:$ff t:$dff t:$dffe t:$dffsr t:$dffsre t:$adff t:$adffe t:$aldff t:$aldffe t:$sdff t:$sdffe t:$sdffce t:$dlatch t:$adlatch t:$dlatchsr t:$_DFFE_NN_ t:$_DFFE_NP_ t:$_DFFE_PN_ t:$_DFFE_PP_ t:$_DFFSR_NNN_ t:$_DFFSR_NNP_ t:$_DFFSR_NPN_ t:$_DFFSR_NPP_ t:$_DFFSR_PNN_ t:$_DFFSR_PNP_ t:$_DFFSR_PPN_ t:$_DFFSR_PPP_ t:$_DFFSRE_NNNN_ t:$_DFFSRE_NNNP_ t:$_DFFSRE_NNPN_ t:$_DFFSRE_NNPP_ t:$_DFFSRE_NPNN_ t:$_DFFSRE_NPNP_ t:$_DFFSRE_NPPN_ t:$_DFFSRE_NPPP_ t:$_DFFSRE_PNNN_ t:$_DFFSRE_PNNP_ t:$_DFFSRE_PNPN_ t:$_DFFSRE_PNPP_ t:$_DFFSRE_PPNN_ t:$_DFFSRE_PPNP_ t:$_DFFSRE_PPPN_ t:$_DFFSRE_PPPP_ t:$_DFF_N_ t:$_DFF_P_ t:$_DFF_NN0_ t:$_DFF_NN1_ t:$_DFF_NP0_ t:$_DFF_NP1_ t:$_DFF_PN0_ t:$_DFF_PN1_ t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_NN0N_ t:$_DFFE_NN0P_ t:$_DFFE_NN1N_ t:$_DFFE_NN1P_ t:$_DFFE_NP0N_ t:$_DFFE_NP0P_ t:$_DFFE_NP1N_ t:$_DFFE_NP1P_ t:$_DFFE_PN0N_ t:$_DFFE_PN0P_ t:$_DFFE_PN1N_ t:$_DFFE_PN1P_ t:$_DFFE_PP0N_ t:$_DFFE_PP0P_ t:$_DFFE_PP1N_ t:$_DFFE_PP1P_ t:$_ALDFF_NN_ t:$_ALDFF_NP_ t:$_ALDFF_PN_ t:$_ALDFF_PP_ t:$_ALDFFE_NNN_ t:$_ALDFFE_NNP_ t:$_ALDFFE_NPN_ t:$_ALDFFE_NPP_ t:$_ALDFFE_PNN_ t:$_ALDFFE_PNP_ t:$_ALDFFE_PPN_ t:$_ALDFFE_PPP_ t:$_SDFF_NN0_ t:$_SDFF_NN1_ t:$_SDFF_NP0_ t:$_SDFF_NP1_ t:$_SDFF_PN0_ t:$_SDFF_PN1_ t:$_SDFF_PP0_ t:$_SDFF_PP1_ t:$_SDFFE_NN0N_ t:$_SDFFE_NN0P_ t:$_SDFFE_NN1N_ t:$_SDFFE_NN1P_ t:$_SDFFE_NP0N_ t:$_SDFFE_NP0P_ t:$_SDFFE_NP1N_ t:$_SDFFE_NP1P_ t:$_SDFFE_PN0N_ t:$_SDFFE_PN0P_ t:$_SDFFE_PN1N_ t:$_SDFFE_PN1P_ t:$_SDFFE_PP0N_ t:$_SDFFE_PP0P_ t:$_SDFFE_PP1N_ t:$_SDFFE_PP1P_ t:$_SDFFCE_NN0N_ t:$_SDFFCE_NN0P_ t:$_SDFFCE_NN1N_ t:$_SDFFCE_NN1P_ t:$_SDFFCE_NP0N_ t:$_SDFFCE_NP0P_ t:$_SDFFCE_NP1N_ t:$_SDFFCE_NP1P_ t:$_SDFFCE_PN0N_ t:$_SDFFCE_PN0P_ t:$_SDFFCE_PN1N_ t:$_SDFFCE_PN1P_ t:$_SDFFCE_PP0N_ t:$_SDFFCE_PP0P_ t:$_SDFFCE_PP1N_ t:$_SDFFCE_PP1P_ t:$_SR_NN_ t:$_SR_NP_ t:$_SR_PN_ t:$_SR_PP_ t:$_DLATCH_N_ t:$_DLATCH_P_ t:$_DLATCH_NN0_ t:$_DLATCH_NN1_ t:$_DLATCH_NP0_ t:$_DLATCH_NP1_ t:$_DLATCH_PN0_ t:$_DLATCH_PN1_ t:$_DLATCH_PP0_ t:$_DLATCH_PP1_ t:$_DLATCHSR_NNN_ t:$_DLATCHSR_NNP_ t:$_DLATCHSR_NPN_ t:$_DLATCHSR_NPP_ t:$_DLATCHSR_PNN_ t:$_DLATCHSR_PNP_ t:$_DLATCHSR_PPN_ t:$_DLATCHSR_PPP_ t:$_FF_