splitnets -driver not behaving as expected.

[thiskappaisgrey]

/* Generated by Yosys 0.38 (git sha1 543faed9c8c, gcc 13.2.0 -fPIC -Os) */

(* top =  1  *)
(* src = "top.sv:1.1-19.10" *)
module top(i_instr, o_out);
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _000_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _001_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _002_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _003_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _004_;
  (* src = "top.sv:13.9-18.12|mycells.v:9.12-9.17" *)
  wire _005_;
  (* src = "top.sv:13.9-18.12|mycells.v:7.7-7.8" *)
  wire _006_;
  (* src = "top.sv:13.9-18.12|mycells.v:7.10-7.11" *)
  wire _007_;
  (* src = "top.sv:13.9-18.12|mycells.v:9.8-9.9" *)
  wire _008_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _009_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _010_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _011_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _012_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _013_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *)
  wire _014_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.7-12.8" *)
  wire _015_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.10-12.11" *)
  wire _016_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.8-13.9" *)
  wire _017_;
  (* src = "top.sv:13.9-18.12|mycells.v:3.12-3.14" *)
  wire _018_;
  (* src = "top.sv:13.9-18.12|mycells.v:2.7-2.8" *)
  wire _019_;
  (* src = "top.sv:13.9-18.12|mycells.v:3.8-3.9" *)
  wire _020_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _021_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _022_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _023_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _024_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _025_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _026_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _027_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _028_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _029_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _030_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *)
  wire _031_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.7-12.8" *)
  wire _032_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.10-12.11" *)
  wire _033_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.8-13.9" *)
  wire _034_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _035_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _036_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _037_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _038_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _039_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _040_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _041_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _042_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _043_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _044_;
  (* src = "top.sv:13.9-18.12|mycells.v:9.12-9.17" *)
  wire _045_;
  (* src = "top.sv:13.9-18.12|mycells.v:7.7-7.8" *)
  wire _046_;
  (* src = "top.sv:13.9-18.12|mycells.v:7.10-7.11" *)
  wire _047_;
  (* src = "top.sv:13.9-18.12|mycells.v:9.8-9.9" *)
  wire _048_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _049_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _050_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _051_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _052_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _053_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *)
  wire _054_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.7-12.8" *)
  wire _055_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.10-12.11" *)
  wire _056_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.8-13.9" *)
  wire _057_;
  (* src = "top.sv:13.9-18.12|mycells.v:3.12-3.14" *)
  wire _058_;
  (* src = "top.sv:13.9-18.12|mycells.v:2.7-2.8" *)
  wire _059_;
  (* src = "top.sv:13.9-18.12|mycells.v:3.8-3.9" *)
  wire _060_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _061_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _062_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _063_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _064_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _065_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _066_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _067_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _068_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _069_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _070_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *)
  wire _071_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.7-12.8" *)
  wire _072_;
  (* src = "top.sv:13.9-18.12|mycells.v:12.10-12.11" *)
  wire _073_;
  (* src = "top.sv:13.9-18.12|mycells.v:13.8-13.9" *)
  wire _074_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *)
  wire _075_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *)
  wire _076_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.7-24.8" *)
  wire _077_;
  (* src = "top.sv:13.9-18.12|mycells.v:24.10-24.11" *)
  wire _078_;
  (* src = "top.sv:13.9-18.12|mycells.v:25.8-25.9" *)
  wire _079_;
  (* src = "top.sv:13.9-18.12|alu.sv:2.20-2.23" *)
  wire _080_;
  (* src = "top.sv:13.9-18.12|alu.sv:2.20-2.23" *)
  wire _081_;
  (* src = "top.sv:13.9-18.12|alu.sv:3.20-3.23" *)
  wire _082_;
  (* src = "top.sv:13.9-18.12|alu.sv:3.20-3.23" *)
  wire _083_;
  (* src = "top.sv:13.9-18.12|alu.sv:4.21-4.30" *)
  wire _084_;
  (* src = "top.sv:13.9-18.12|alu.sv:4.21-4.30" *)
  wire _085_;
  wire _086_;
  wire _087_;
  wire _088_;
  wire _089_;
  wire _090_;
  wire _091_;
  wire _092_;
  wire _093_;
  wire _094_;
  wire _095_;
  wire _096_;
  wire _097_;
  wire _098_;
  wire _099_;
  wire _100_;
  wire _101_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:597.13-597.25|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire _102_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:597.13-597.25|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire _103_;
  (* src = "top.sv:13.9-18.12|alu.sv:13.22-13.31" *)
  wire [1:0] _104_;
  wire _105_;
  wire _106_;
  wire _107_;
  wire [1:0] _108_;
  wire _109_;
  wire [1:0] _110_;
  wire _111_;
  wire [1:0] _112_;
  wire _113_;
  wire _114_;
  wire [1:0] _115_;
  wire [1:0] _116_;
  wire [1:0] _117_;
  wire _118_;
  wire _119_;
  wire _120_;
  (* src = "top.sv:13.9-18.12|alu.sv:11.22-11.34" *)
  wire [1:0] _121_;
  (* src = "top.sv:13.9-18.12|alu.sv:11.24-11.33" *)
  wire [1:0] _122_;
  wire _123_;
  wire _124_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:569.20-569.21|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _125_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:571.28-571.29|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [7:0] _126_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:583.28-583.35|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [7:0] _127_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:589.23-589.33|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [3:0] _128_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:589.23-589.33|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [3:0] _129_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:573.22-573.23|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [3:0] _130_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:575.21-575.22|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _131_;
  (* force_downto = 32'd1 *)
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:578.19-578.22|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _132_;
  wire _133_;
  wire _134_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:585.44-585.84|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _135_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:585.44-585.84|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _136_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:585.44-585.84|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _137_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:585.44-585.84|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _138_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:593.20-593.31|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire _139_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:593.20-593.31|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire _140_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:597.13-597.15|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire _141_;
  (* src = "top.sv:13.9-18.12|/nix/store/w00g6c95q8b6mv33zfy90803igk26pkn-yosys-0.38/bin/../share/yosys/techmap.v:597.13-597.25|alu.sv:9.5-14.12|alu.sv:0.0-0.0" *)
  wire [1:0] _142_;
  (* src = "top.sv:13.9-18.12|alu.sv:10.22-10.31" *)
  wire [1:0] _143_;
  (* hdlname = "alu i_a" *)
  (* src = "top.sv:13.9-18.12|alu.sv:2.20-2.23" *)
  wire [1:0] \alu.i_a ;
  (* hdlname = "alu i_b" *)
  (* src = "top.sv:13.9-18.12|alu.sv:3.20-3.23" *)
  wire [1:0] \alu.i_b ;
  (* hdlname = "alu i_control" *)
  (* src = "top.sv:13.9-18.12|alu.sv:4.21-4.30" *)
  wire [1:0] \alu.i_control ;
  (* hdlname = "alu o_res" *)
  (* src = "top.sv:13.9-18.12|alu.sv:5.22-5.27" *)
  wire [1:0] \alu.o_res ;
  (* hdlname = "decoder i_instr" *)
  (* src = "top.sv:8.13-12.12|decoder.sv:3.21-3.28" *)
  wire [5:0] \decoder.i_instr ;
  (* hdlname = "decoder o_a" *)
  (* src = "top.sv:8.13-12.12|decoder.sv:5.22-5.25" *)
  wire [1:0] \decoder.o_a ;
  (* hdlname = "decoder o_b" *)
  (* src = "top.sv:8.13-12.12|decoder.sv:6.22-6.25" *)
  wire [1:0] \decoder.o_b ;
  (* hdlname = "decoder o_op" *)
  (* src = "top.sv:8.13-12.12|decoder.sv:4.22-4.26" *)
  wire [1:0] \decoder.o_op ;
  (* src = "top.sv:2.27-2.34" *)
  input [5:0] i_instr;
  wire [5:0] i_instr;
  (* src = "top.sv:6.17-6.20" *)
  wire [1:0] o_a;
  (* src = "top.sv:7.17-7.20" *)
  wire [1:0] o_b;
  (* src = "top.sv:5.17-5.21" *)
  wire [1:0] o_op;
  (* src = "top.sv:3.28-3.33" *)
  output [1:0] o_out;
  wire [1:0] o_out;
  assign _000_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _001_;
  assign _001_ = _002_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _003_;
  assign _005_ = _006_ ^ (* src = "top.sv:13.9-18.12|mycells.v:9.12-9.17" *) _007_;
  assign _009_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _010_;
  assign _010_ = _011_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _012_;
  assign _014_ = _015_ & (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *) _016_;
  assign _018_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:3.12-3.14" *) _019_;
  assign _021_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _022_;
  assign _022_ = _023_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _024_;
  assign _026_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _027_;
  assign _027_ = _028_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _029_;
  assign _031_ = _032_ & (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *) _033_;
  assign _035_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _036_;
  assign _036_ = _037_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _038_;
  assign _040_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _041_;
  assign _041_ = _042_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _043_;
  assign _045_ = _046_ ^ (* src = "top.sv:13.9-18.12|mycells.v:9.12-9.17" *) _047_;
  assign _049_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _050_;
  assign _050_ = _051_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _052_;
  assign _054_ = _055_ & (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *) _056_;
  assign _058_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:3.12-3.14" *) _059_;
  assign _061_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _062_;
  assign _062_ = _063_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _064_;
  assign _066_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _067_;
  assign _067_ = _068_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _069_;
  assign _071_ = _072_ & (* src = "top.sv:13.9-18.12|mycells.v:13.12-13.17" *) _073_;
  assign _075_ = ~ (* src = "top.sv:13.9-18.12|mycells.v:25.12-25.20" *) _076_;
  assign _076_ = _077_ | (* src = "top.sv:13.9-18.12|mycells.v:25.14-25.19" *) _078_;
  assign \decoder.o_a  = \decoder.i_instr [3:2];
  assign \decoder.o_b  = \decoder.i_instr [5:4];
  assign \decoder.o_op  = \decoder.i_instr [1:0];
  assign \decoder.i_instr  = i_instr;
  assign o_a = \decoder.o_a ;
  assign o_b = \decoder.o_b ;
  assign o_op = \decoder.o_op ;
  assign _125_ = 2'hx;
  assign _126_ = { _143_, _121_, _122_, _104_ };
  assign _130_ = { _124_, _123_, _134_, _133_ };
  assign _131_ = \alu.o_res ;
  assign \alu.o_res  = _142_;
  assign _127_[1:0] = _135_;
  assign _127_[3:2] = _136_;
  assign _127_[5:4] = _137_;
  assign _127_[7:6] = _138_;
  assign _128_[0] = _127_[0];
  assign _128_[1] = _127_[2];
  assign _128_[2] = _127_[4];
  assign _128_[3] = _127_[6];
  assign _132_[0] = _139_;
  assign _129_[0] = _127_[1];
  assign _129_[1] = _127_[3];
  assign _129_[2] = _127_[5];
  assign _129_[3] = _127_[7];
  assign _132_[1] = _140_;
  assign _142_[0] = _102_;
  assign _084_ = \alu.i_control [0];
  assign _085_ = \alu.i_control [1];
  assign _142_[1] = _103_;
  assign _080_ = \alu.i_a [0];
  assign _082_ = \alu.i_b [0];
  assign _081_ = \alu.i_a [1];
  assign _083_ = \alu.i_b [1];
  assign _079_ = _075_;
  assign _077_ = _095_;
  assign _078_ = _100_;
  assign _103_ = _079_;
  assign _074_ = _071_;
  assign _072_ = _097_;
  assign _073_ = _099_;
  assign _100_ = _074_;
  assign _070_ = _066_;
  assign _068_ = _093_;
  assign _069_ = _098_;
  assign _099_ = _070_;
  assign _065_ = _061_;
  assign _063_ = _085_;
  assign _064_ = _081_;
  assign _098_ = _065_;
  assign _060_ = _058_;
  assign _059_ = _096_;
  assign _097_ = _060_;
  assign _057_ = _054_;
  assign _055_ = _085_;
  assign _056_ = _083_;
  assign _096_ = _057_;
  assign _053_ = _049_;
  assign _051_ = _081_;
  assign _052_ = _094_;
  assign _095_ = _053_;
  assign _048_ = _045_;
  assign _046_ = _084_;
  assign _047_ = _083_;
  assign _094_ = _048_;
  assign _044_ = _040_;
  assign _042_ = _084_;
  assign _043_ = _083_;
  assign _093_ = _044_;
  assign _039_ = _035_;
  assign _037_ = _087_;
  assign _038_ = _092_;
  assign _102_ = _039_;
  assign _034_ = _031_;
  assign _032_ = _089_;
  assign _033_ = _091_;
  assign _092_ = _034_;
  assign _030_ = _026_;
  assign _028_ = _101_;
  assign _029_ = _090_;
  assign _091_ = _030_;
  assign _025_ = _021_;
  assign _023_ = _085_;
  assign _024_ = _080_;
  assign _090_ = _025_;
  assign _020_ = _018_;
  assign _019_ = _088_;
  assign _089_ = _020_;
  assign _017_ = _014_;
  assign _015_ = _085_;
  assign _016_ = _082_;
  assign _088_ = _017_;
  assign _013_ = _009_;
  assign _011_ = _080_;
  assign _012_ = _086_;
  assign _087_ = _013_;
  assign _008_ = _005_;
  assign _006_ = _084_;
  assign _007_ = _082_;
  assign _086_ = _008_;
  assign _004_ = _000_;
  assign _002_ = _084_;
  assign _003_ = _082_;
  assign _101_ = _004_;
  assign \alu.i_a  = o_a;
  assign \alu.i_b  = o_b;
  assign \alu.i_control  = o_op;
  assign o_out = \alu.o_res ;
endmodule

When I load this file into yosys and run this script:

hierarchy -check -top top;
splice; splitnets -driver;

I expect that the piecewise assignments, e.g.:

  assign _132_[0] = _139_;
  assign _129_[0] = _127_[1];
  assign _129_[1] = _127_[3];
  assign _129_[2] = _127_[5];
  assign _129_[3] = _127_[7];
  assign _132_[1] = _140_;
  assign _142_[0] = _102_;

go away, but they don't. I'm I misunderstanding what the pass should do? Or I'm I misusing the pass?

@gussmith23 (I'm collaborating with him) @jix

[gussmith23]

For a little context: I spoke with @jix about this; they suggested splice; splitnets -driver as a way to get rid of any assignments that look like

assign signal[...] = ...

[nakengelhardt]

Those wires are both undriven and unused, just run clean to get rid of them.

splitnets -driver says "split nets so that no driver drives only part of a net" so it won't do anything to undriven wires.
splice says "selected output wires and all cell ports of selected cells driven by selected wires are rewired" so that doesn't affect unused wires.

[gussmith23]

that makes so much sense -- we were wondering why running opt made these go away. it's because they get cleaned up!