Outputs differ before and after synthesis, but Yosys seems correct.

[Noah-S-E]

Version

Yosys 0.39+165

On which OS did this happen?

Linux

Reproduction Steps

Hello, the outputs before and after synthesis are inconsistent when performing bitwise operations on signed numbers in Verilog using Yosys. However, it seems that Yosys provided the correct output.

Given my original design, when the input wire1 is 6'b110011, the for loop should execute, and the if condition should be true, resulting in the output y being 01. However, simulation results show that the original design outputs 00, while the synthesized design outputs 01.

module top  (y, clk, wire1);
  output wire [1:0] y;
  input wire clk;
 input wire signed [5:0] wire1;  

  reg signed [1:0] forvar7 = 2'b00;  
  reg signed [6:0] forvar5 = 7'b0000000;  

  
  assign y = {forvar7};
  
  always
    @(posedge clk) 
    begin
      for (forvar5 = (7'b0000000); (forvar5 < (7'b0000001)); forvar5 = (forvar5 + (7'b0000001)))
        begin
          if ( (^(forvar5 + wire1) ? forvar5 : wire1) )
            begin
		          forvar7 = (2'b01);
            end
        end
    end
endmodule

The testbench is as follows：

`include "rtl.v"

module testbench;

  reg clk;
  reg signed [5:0] wire1;
  wire [1:0] y;


  top uut (
    .y(y),
    .clk(clk),
    .wire1(wire1)
  );


  initial begin
    clk = 0;
    forever #5 clk = ~clk; 
  end


  initial begin
 
    wire1 = 6'b110011;

 
    #10;
    $display("At time %t, y = %b", $time, y);

 
    #20;
    $finish;
  end
endmodule

yosys_5_15.zip

Expected Behavior

I think the yosys tool is correct, but why does it output inconsistent

Actual Behavior

Inconsistent output before and after synthesis