Replace modules with internal cells, like $sr

[Rodrigodd]

Some time ago, I asked on Slack how I could replace a module in a design with a $sr cell, but I never got a response. It took me a while to figure it out, so I thought it would be worth documenting that here.

Basically, I have a Verilog module that simulates an SR-latch, but when this module is parsed by Yosys, it is translated into a combinatorial circuit driving a $latch cell. When translated back to Verilog and simulated, it would misbehave due to the order of signal evaluation.

To avoid that, I needed to replace the entire module with a single $sr, which translates much better back to Verilog. Below is how I did that.

For example, let's say the design has the following module:

module seq_rs_latch (input nr, s, output q);
    reg val;
    initial val = 1'b0;

    always @(*) begin
        if (~nr) val = 1'b0;
        else if (s) val = 1'b1;
    end

    assign q = val;
endmodule

One way to resolve this is to edit the module implementation to use a direct instance of the $sr cell and remember to pass the -icells option to Yosys. However, if changing the original design is undesirable (since it would only work on Yosys), we can create a new module with the same signature as the original and automatically replace it in the design using chtype.

So, you can create a module like this:

module mysr (input nr, s, output q );
    $sr #(
        .SET_POLARITY(1'b1),
        .CLR_POLARITY(1'b0),
        .WIDTH(1)
    ) sr1 (
        .CLR(nr),
        .SET(s),
        .Q(q)
    );
endmodule

And then replace it in the original design:

read_verilog original_design.v
hierarchy -top SM83Core

# We can write the Verilog module directly in the Yosys script file/command line.
read_verilog -icells <<EOT
module mysr (input nr, s, output q );
    $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(1)) sr1 (.CLR(nr), .SET(s), .Q(q));
endmodule
EOT

chtype -map seq_rs_latch mysr

You can do the same for any other internal cell. You only need to figure out the name of the output ports and parameters it requires. One way to figure this out is by checking InternalCellChecker::check in kernel/rtlil.cc.

In case the circuit you need to replace is not nicely contained in a module, you can use extract to isolate it into its own module and then later replace the module with one that uses the internal cell. I couldn't think of an illustrative example, but you can see it in action here.