Techmapping to Infer Parameters

[malifarooq]

This is part of an OpenFPGA project. I am trying to infer different parametrizations of a hard logic block in the .blif file via Yosys Techmap without having parameters in the top level RTL. (E.g. Having add6(a,b) being mapped to adder #(.MODE(6)) (a,b))
However my current efforts keep failing with the following error:
ERROR: Can't find object for defparam 'MODE'

Here is what I'm doing:

The top level module instantiated as:

module top(...);
(* keep *)
super_mod mod2 ( ...);

endmodule

The following RTL provided as lib:

(* whitebox *)
module super_mod(....);
parameter MODE = 2'b00;

_dummy functionality here_
endmodule

Finally the map file:

(* techmap_celltype = "super_mod" *)
module top_secret(....);
   super_mod #(.MODE(2'b00)) _TECHMAP_REPLACE_ (...);
endmodule

The script looks something like:

read_verilog  top.v
read_verilog -lib -specify /path/to/lib.v
hierarchy -top top
proc
techmap -map /path/to/map_file.v

Am I missing something? Any help would be greatly appreciated!

[KrystalDelusion]

I'm not very familiar with techmap, but the error you're seeing is raised when trying to assign a parameter to a module which doesn't have that parameter. I think this might be something to do with the names of modules? The following appears to work correctly:

read_verilog <<EOF
module top();
(* keep *)
top_secret mod2 ();

endmodule
EOF

read_verilog -lib -specify <<EOF
(* whitebox *)
module super_mod();
parameter MODE = 2'b00;

/*_dummy functionality here_*/
endmodule
EOF

hierarchy -top top
proc
techmap -map <<EOF
module top_secret();
   super_mod #(.MODE(2'b00)) _TECHMAP_REPLACE_ ();
endmodule
EOF

stat

This maps the top_secret module in top so that the final stat call shows a single super_mod cell.

Changing the name of the whitebox module to actual_mod, and updating the techmap file to match also works:

read_verilog <<EOF
module top();
(* keep *)
super_mod mod2 ();

endmodule
EOF

read_verilog -lib -specify <<EOF
(* whitebox *)
module actual_mod();
parameter MODE = 2'b00;

/*_dummy functionality here_*/
endmodule
EOF

hierarchy -top top
proc
debug techmap -map <<EOF
(* techmap_celltype = "super_mod" *)
module top_secret();
   actual_mod #(.MODE(2'b00)) _TECHMAP_REPLACE_ ();
endmodule
EOF

stat

[malifarooq]

This works! Thank you!