SystemVerilog procedural assignments within expressions

[imlibra]

Version

“unexpected TOK_INCREMENT” when SystemVerilog source contains ++

On which OS did this happen?

Linux

Reproduction Steps

yosys -read -sv hamming/hamming_dec.sv

Expected Behavior

……

Actual Behavior

-- Parsing hamming/hamming_dec.sv' using frontend -sv' --

1. Executing Verilog-2005 frontend: hamming/hamming_dec.sv
   Parsing SystemVerilog input from `hamming/hamming_dec.sv' to AST representation.
   hamming/hamming_parameters.svh:57: ERROR: syntax error, unexpected TOK_INCREMENT

[Ravenslofty]

The line in question is generate_permutation[cDBITS + k++] = i;, which I think is a bit more specific than just "when SystemVerilog source contains ++"; for example if Yosys didn't like ++ it'd have errored elsewhere.

[zachjs]

I'm interested in adding support for assignment expressions to Yosys, but it's not something I'm currently working on. In the meantime, you could use https://github.com/zachjs/sv2v, which already supports this feature.

[zachjs]

@imlibra If you have the time, please try out my patch in #3920, which adds support for assignments within expressions.