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Discrepancy what happens on read -vlog2k; hierarchy; depending on Verific presence #4203

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povik opened this issue Feb 12, 2024 · 3 comments
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pending-verification This issue is pending verification and/or reproduction

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@povik
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povik commented Feb 12, 2024

Version

Yosys 0.37+74 (git sha1 c9f842f41, clang++ 11.1.0 -fPIC -Os)

On which OS did this happen?

macOS

Reproduction Steps

read -vlog2k <<EOF
module top;
	wire [3:0] w = 4;
endmodule
EOF
hierarchy
stat

Expected Behavior

No matter if I am running Yosys with Verific or without, by the time the stat command is reached the module is fully elaborated and lowered to RTLIL.

Actual Behavior

Without Verific, the module stays at $abstract\top even past the hierarchy command. If I do hierarchy -top top instead, then the module does get lowered.

With Verific, Yosys has the expected behavior.

@povik povik added the pending-verification This issue is pending verification and/or reproduction label Feb 12, 2024
@povik
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povik commented Feb 12, 2024

Not sure if this is an actual issue. I assume the target with the read command that switches between the two Verilog frontends is consistent behavior on appropriately written scripts, and I don't know if it's defined what those are. In any case this behavior surprised me.

@nakengelhardt
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Isn't that what we fixed with #4130? Have you tried with latest master?

@povik
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povik commented Feb 13, 2024

Isn't that what we fixed with #4130?

Indeed looks like it. It doesn't reproduce on latest master.

@povik povik closed this as not planned Won't fix, can't repro, duplicate, stale Feb 13, 2024
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