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Efficient handling of patterns emitted by sv2v #4615
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Amaranth lowers such constructs into |
yosys-slang uses |
Good to know because I would have informed Robert next week as well, so there is no need. In general I think this is worth solving because the alternative, ensuring no other tool produces similar constructs, does not seem feasible to me. |
(Robert?) |
Sorry, Rob Taylor. |
I have no objection to the premise of handling these patterns more efficiently in general, but insofar as sv2v targets yosys, I really don't intend for its output to be pathological. Detecting this pattern doesn't seem hard. (Any time a variable is used to index into something multi-dimensional?) Then adding the appropriate read/write attribute to the declaration seems harmless, if we go that route. Adding a temporary would be a bit more complex but also doable. |
Feature Description
The external tool sv2v rewrites member accesses, element selects and other operations into part-selects and a bit of arithmetic.
Take e.g. (source)
it gets rewritten into
Within the read_verilog frontend, this gets parsed as a shift cell with the shift amount driven by arithmetic cells. Notwithstanding
peepopt
transformations some of those shift cells survive to thetechmap
stage at which time they are expanded into a sea of mux gates. Due to the presence of constant bits most of those gates are redundant as evinced by subsequentopt_expr -mux_undef
cleaning them up. This redundant mux effect can be so bad it accounts for >80 % of Yosys peak memory usage in a real world synthesis flow incorporating sv2v.This can get addressed at different points:
opt_expr
rules which transform a shift cell with constant bits on some of its inputstechmap
provided second-order constant propagation isn't a significant factorCc @zachjs @phsauter
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