Corrected wrong validation of spectre attack

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Ziang95 · Dec 12, 2019 · 1d0ec55 · 1d0ec55
1 parent 96bb66e
commit 1d0ec55
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Showing 66 changed files with 138 additions and 3,426 deletions.
diff --git a/FU.cpp b/FU.cpp
@@ -1,4 +1,4 @@
-#include "FU.h"
+#include ".\headers\FU.h"
 
 extern config *CPU_cfg;
 extern instr_queue *instr_Q;
@@ -239,8 +239,19 @@ A:      at_rising_edge(next_vdd);
                         {
                             if (branch == tmp->taken)
                             {
-                                at_falling_edge(next_vdd);
-                                R->finished = true;
+                                if (tmp->taken && tmp->target != R->instr_i + 1 + task.offset)
+                                {
+                                    tmp->target = R->instr_i + 1 +task.offset;
+                                    brcUnit.to_target(R->instr_i + 1 + task.offset);
+                                    msg_log("Begin Squash", 3);
+                                    brcUnit.to_squash(task.dest);   
+                                    at_falling_edge(next_vdd);
+                                }
+                                else
+                                {
+                                    at_falling_edge(next_vdd);
+                                    R->finished = true;
+                                }
                             }
                             else
                             {
@@ -258,7 +269,7 @@ A:      at_rising_edge(next_vdd);
                         {
                             if (branch)
                             {
-                                CPU_BTB.addEntry(R->instr_i, (R->instr_i + 1 + task.offset)%8);
+                                CPU_BTB.addEntry(R->instr_i, R->instr_i + 1 + task.offset);
                                 brcUnit.to_target(R->instr_i + 1 + task.offset);
                                 msg_log("Begin Squash", 3);
                                 brcUnit.to_squash(task.dest);

diff --git a/ROB.cpp b/ROB.cpp
@@ -1,4 +1,4 @@
-#include "ROB.h"
+#include ".\headers\ROB.h"
 
 extern config *CPU_cfg;
 extern instr_queue *instr_Q;

diff --git a/branch.cpp b/branch.cpp
@@ -1,5 +1,5 @@
-#include "branch.h"
-#include "clock.h"
+#include ".\headers\branch.h"
+#include ".\headers\clock.h"
 
 extern unordered_map <string, int> RAT;
 extern vector<int*> clk_wait_list;

diff --git a/branch.h b/branch.h
@@ -16,7 +16,7 @@ typedef struct squash_param
     bool flag = false;          //Whether the squash has begun
 }squash_param;
 
-#include "mips.h"
+#include ".\headers\mips.h"
 
 class BTB
 {

diff --git a/clock.cpp b/clock.cpp
@@ -1,4 +1,4 @@
-#include "clock.h"
+#include ".\headers\clock.h"
 
 extern vector<int*> clk_wait_list;
 extern int debug_level;

diff --git a/FU.h → headers/FU.h b/FU.h → headers/FU.h
diff --git a/ROB.h → headers/ROB.h b/ROB.h → headers/ROB.h
diff --git a/headers/branch.h b/headers/branch.h
@@ -0,0 +1,48 @@
+#ifndef BRANCH_H
+#define BRANCH_H
+
+typedef struct BTBEntry
+{
+    int target;
+    bool predicted;
+    bool taken;
+}BTBEntry;
+
+typedef struct squash_param
+{
+    int R_f;                    //The front pointer of ROB
+    int R_r;                    //The rear pointer of ROB
+    int ROB_i;                  //The affected ROB index
+    bool flag = false;          //Whether the squash has begun
+}squash_param;
+
+#include "mips.h"
+
+class BTB
+{
+    private:
+        BTBEntry buf[BTB_LEN];
+    public:
+        BTB();
+        void addEntry(int _instr_i, int _target);
+        BTBEntry *getEntry(int instr_i);
+};
+
+class branchCtrl
+{
+    private:
+        int ROB_i;
+        int target;
+    public:
+        pthread_t handle;
+        int next_vdd;
+        branchCtrl();
+        void to_squash(int _ROB_i);
+        void to_target(int _target);
+        int squash_ROB_i();
+        void branch_automat();
+};
+
+void init_brcUnit();
+
+#endif
diff --git a/clock.h → headers/clock.h b/clock.h → headers/clock.h
diff --git a/import.h → headers/import.h b/import.h → headers/import.h
diff --git a/instruction.h → headers/instruction.h b/instruction.h → headers/instruction.h
diff --git a/issue.h → headers/issue.h b/issue.h → headers/issue.h
diff --git a/memory.h → headers/memory.h b/memory.h → headers/memory.h
diff --git a/mips.h → headers/mips.h b/mips.h → headers/mips.h
diff --git a/output.h → headers/output.h b/output.h → headers/output.h
diff --git a/registor.h → headers/registor.h b/registor.h → headers/registor.h
diff --git a/reserv_station.h → headers/reserv_station.h b/reserv_station.h → headers/reserv_station.h
diff --git a/import.cpp b/import.cpp
@@ -1,4 +1,4 @@
-#include "import.h"
+#include ".\headers\import.h"
 
 extern config *CPU_cfg;
 extern clk_tick sys_clk;

diff --git a/instruction.cpp b/instruction.cpp
@@ -1,4 +1,4 @@
-#include "instruction.h"
+#include ".\headers\instruction.h"
 
 instr_queue::instr_queue(vector<instr> a):
 Q(a),size(a.size())

diff --git a/issue.cpp b/issue.cpp
@@ -1,4 +1,4 @@
-#include "issue.h"
+#include ".\headers\issue.h"
 
 extern pthread_t iss_unit;
 extern clk_tick sys_clk;
@@ -264,7 +264,7 @@ void *issue_automat(void *arg)
                     if (BTBEntry* predctr = CPU_BTB.getEntry(R->instr_i))
                     {
                         if (predctr->taken)
-                            instr_Q->move_ptr(((R->instr_i)/8)*8 + predctr->target);
+                            instr_Q->move_ptr(((R->instr_i)/8)*8 + (predctr->target)%8);
                         else
                             instr_Q->ptr_advance();
                     }

diff --git a/memory.cpp b/memory.cpp
@@ -1,4 +1,4 @@
-#include "memory.h"
+#include ".\headers\memory.h"
 
 extern clk_tick sys_clk;
 extern memory main_mem;

diff --git a/mips.cpp b/mips.cpp
@@ -1,4 +1,4 @@
-#include "mips.h"
+#include ".\headers\mips.h"
 
 config *CPU_cfg = nullptr;
 instr_queue *instr_Q = nullptr;

diff --git a/output.cpp b/output.cpp
@@ -1,4 +1,4 @@
-#include "output.h"
+#include ".\headers\output.h"
 
 using namespace std;
 

diff --git a/registor.cpp b/registor.cpp
@@ -1,4 +1,4 @@
-#include "registor.h"
+#include ".\headers\registor.h"
 
 extern clk_tick sys_clk;
 

diff --git a/reserv_station.cpp b/reserv_station.cpp
@@ -1,5 +1,5 @@
-#include "reserv_station.h"
-#include "mips.h"
+#include ".\headers\reserv_station.h"
+#include ".\headers\mips.h"
 
 extern config *CPU_cfg;
 extern clk_tick sys_clk;

diff --git a/victim_code.txt → test_case/attacked_code.txt b/victim_code.txt → test_case/attacked_code.txt
diff --git a/tumasulu/test_cases/example_Case1.txt → test_case/case1.txt b/tumasulu/test_cases/example_Case1.txt → test_case/case1.txt
diff --git a/test_case/case10.txt b/test_case/case10.txt
@@ -0,0 +1,17 @@
+  # of rs Cycles in EX  Cycles in Mem # of FUs
+Integer adder 2 1   1
+FP adder  3 3   1
+FP multiplier 2 20    1
+Load/store unit 3 1 4 1
+ROB entries = 128
+CDB buffer entries = 1
+R1=10,R2=16,R3=30,F1=111.111,F2=222.222
+Mem[4]=1,Mem[8]=2,Mem[12]=3.4
+
+ADD R1,R0,R0
+SD F1, 0(R1)
+ADDI R1,R1,4
+BNE R1,R2,-3
+SD F2, 0(R1)
+LD F3, 0(R1)
+LD F4, -8(R1)
diff --git a/tumasulu/test_cases/example_Case12.txt → test_case/case11.txt b/tumasulu/test_cases/example_Case12.txt → test_case/case11.txt
diff --git a/tumasulu/test_cases/example_Case2.txt → test_case/case2.txt b/tumasulu/test_cases/example_Case2.txt → test_case/case2.txt
diff --git a/tumasulu/test_cases/example_Case3.txt → test_case/case3.txt b/tumasulu/test_cases/example_Case3.txt → test_case/case3.txt
diff --git a/tumasulu/test_cases/example_Case4.txt → test_case/case4.txt b/tumasulu/test_cases/example_Case4.txt → test_case/case4.txt
diff --git a/tumasulu/test_cases/example_Case5.txt → test_case/case5.txt b/tumasulu/test_cases/example_Case5.txt → test_case/case5.txt
diff --git a/tumasulu/test_cases/example_Case6.txt → test_case/case6.txt b/tumasulu/test_cases/example_Case6.txt → test_case/case6.txt
diff --git a/tumasulu/test_cases/example_Case7.txt → test_case/case7.txt b/tumasulu/test_cases/example_Case7.txt → test_case/case7.txt
diff --git a/tumasulu/test_cases/example_Case8.txt → test_case/case8.txt b/tumasulu/test_cases/example_Case8.txt → test_case/case8.txt
diff --git a/tumasulu/test_cases/example_Case9.txt → test_case/case9.txt b/tumasulu/test_cases/example_Case9.txt → test_case/case9.txt
diff --git a/test_case/the_test_case.txt b/test_case/the_test_case.txt
@@ -0,0 +1,20 @@
+                # of rs         Cycles in EX    Cycles in Mem   # of FUs
+Integer adder   4               1                               1
+FP adder        3               4                               1
+FP multiplier   2               15                              1
+Load/store unit 10              1               5               1
+ROB entries = 64
+CDB buffer entries = 1
+
+R1=12, R2=32, F20=3.0
+Mem[4]=3.0, Mem[8]=2.0, Mem[12]=1.0, Mem[24]=6.0, Mem[28]=5.0, Mem[32]=4.0
+
+ld F2, 0(R1)
+mult.d F4, F2, F20
+ld F6, 0(R2)
+add.d F6, F4, F6
+sd F6, 0(R2)
+addi R1, R1, -4
+addi R2, R2, -4
+bne R1, R0, -8
+NOP
diff --git a/test_case/victim_code.txt b/test_case/victim_code.txt
@@ -0,0 +1,23 @@
+            # of rs Cycles in EX Cycles in Mem # of FUs
+Integer adder	    4	1		1
+FP adder	        3	4		1
+FP multiplier	    2	15		1
+Load/store unit	    3	1	5	1
+ROB entries = 64 
+CDB buffer entries = 1
+
+R0=0
+Mem[4]=3.0
+
+Addi R2, R0, -2
+Addi R3, R0, 4
+Addi R2, R2, 2
+Ld F1, 0(R1)
+Beq R2, R0, 5
+Addi R3, R3, 4
+Addi R2, R2, 8
+Mult.d F3, F2, F1
+Add R2, R2, R2
+Add R1, R1, R1
+Add R1, R1, R1
+Add R1, R1, R1
diff --git a/tumasulu/.gitignore b/tumasulu/.gitignore
diff --git a/tumasulu/ExeTable.h b/tumasulu/ExeTable.h