small fixes, turn off TODO panics in cart.zig (#39)

ZigEmbeddedGroup · May 14, 2024 · 5106eae · 5106eae
1 parent cbb8aa9
commit 5106eae
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Showing 3 changed files with 28 additions and 45 deletions.
diff --git a/src/badge.zig b/src/badge.zig
@@ -88,61 +88,52 @@ pub fn main() !void {
     // MPU.RBAR_A2
     // MPU.RASR_A2
     // MPU.CTRL
-    //
-    // cart init
-    //  pins
-    //  bss
-    //  data
-
-    // After this section of code runs we'll have the following clock setup:
-    // FDLL (48MHz)    => GCLK2 (1MHz)
-    // GCLK2 (1MHz)    => DPLL0 (120MHz)
-    //                 => ADC0 (1MHz)
-    //                 => TC0 (1MHz)
-    //                 => TC1 (1MHz)
-    // DPLL0 (120MHz)  => GCLK0 (120MHz)
-    //
-    // FDLL (48MHz)    => GCLK1 (76.8KHz)
-    // GCLK1 (76.8KHz) => DPLL1 (8.467MHz)
-    // DPLL1 (8.467MHz => GCLK3 (8.467MHz)
-    // GCLK3 (8.467MHz => TC4 (8.467MHz)
 
     // GCLK0 feeds the CPU so put it on OSCULP32K for now
-    clocks.gclk.enable_generator(.GCLK0, .OSCULP32K, .{
-        .divsel = .DIV1,
-        .div = 1,
-    });
+    clocks.gclk.enable_generator(.GCLK0, .OSCULP32K, .{});
 
+    // Enable the first chain of clock generators:
+    //
+    // FDLL (48MHz) => GCLK2 (1MHz) => DPLL0 (120MHz) => GCLK0 (120MHz)
+    //                              => ADC0 (1MHz)
+    //                              => TC0 (1MHz)
+    //                              => TC1 (1MHz)
+    //
     clocks.gclk.enable_generator(.GCLK2, .DFLL, .{
         .divsel = .DIV1,
         .div = 48,
     });
 
-    clocks.gclk.enable_generator(.GCLK1, .DFLL, .{
-        .divsel = .DIV1,
-        .div = 625,
-    });
-
     clocks.enable_dpll(0, .GCLK2, .{
         .factor = 1,
         .input_freq_hz = 1_000_000,
         .output_freq_hz = 120_000_000,
     });
 
+    clocks.gclk.set_peripheral_clk_gen(.GCLK_ADC0, .GCLK2);
+    clocks.gclk.set_peripheral_clk_gen(.GCLK_TC0_TC1, .GCLK2);
+    clocks.gclk.enable_generator(.GCLK0, .DPLL0, .{});
+
+    // The second chain of clock generators:
+    //
+    // FDLL (48MHz) => GCLK1 (76.8KHz) => DPLL1 (8.467MHz) => GCLK3 (8.467MHz) => TC4 (8.467MHz)
+    //
+
+    // The we use GCLK1 here because it's able to divide much more than the
+    // other generators, the other generators max out at 512
+    clocks.gclk.enable_generator(.GCLK1, .DFLL, .{
+        .divsel = .DIV1,
+        .div = 625,
+    });
+
     clocks.enable_dpll(1, .GCLK1, .{
         .factor = 12,
         .input_freq_hz = 76_800,
         .output_freq_hz = 8_467_200,
     });
 
-    clocks.gclk.enable_generator(.GCLK0, .DPLL0, .{
-        .divsel = .DIV1,
-        .div = 1,
-    });
-
-    clocks.gclk.set_peripheral_clk_gen(.GCLK_ADC0, .GCLK1);
-    clocks.gclk.set_peripheral_clk_gen(.GCLK_TC0_TC1, .GCLK1);
-    clocks.gclk.set_peripheral_clk_gen(.GCLK_TC4_TC5, .GCLK2);
+    clocks.gclk.enable_generator(.GCLK3, .DPLL1, .{});
+    clocks.gclk.set_peripheral_clk_gen(.GCLK_TC4_TC5, .GCLK3);
 
     timer.init();
     init_frame_sync();

diff --git a/src/badge/cart.zig b/src/badge/cart.zig
@@ -198,57 +198,49 @@ fn blit(sprite: [*]const User(u8), x: i32, y: i32, rest: *const extern struct {
     _ = x;
     _ = y;
     _ = rest;
-    @panic("TODO");
 }
 
 pub fn oval(x: i32, y: i32, width: u32, height: u32) callconv(.C) void {
     _ = x;
     _ = y;
     _ = width;
     _ = height;
-    @panic("TODO");
 }
 
 pub fn rect(x: i32, y: i32, width: u32, height: u32) callconv(.C) void {
     _ = x;
     _ = y;
     _ = width;
     _ = height;
-    @panic("TODO");
 }
 
 pub fn text(str: [*]const User(u8), len: usize, x: i32, y: i32) callconv(.C) void {
     _ = str;
     _ = len;
     _ = x;
     _ = y;
-    @panic("TODO");
 }
 
 pub fn vline(x: i32, y: i32, len: u32) callconv(.C) void {
     _ = x;
     _ = y;
     _ = len;
-    @panic("TODO");
 }
 
 pub fn hline(x: i32, y: i32, len: u32) callconv(.C) void {
     _ = x;
     _ = y;
     _ = len;
-    @panic("TODO");
 }
 
 pub fn tone(frequency: u32, duration: u32, volume: u32, flags: u32) callconv(.C) void {
     _ = frequency;
     _ = duration;
     _ = volume;
     _ = flags;
-    @panic("TODO");
 }
 
 pub fn trace(str: [*]const User(u8), len: usize) callconv(.C) void {
     _ = str;
     _ = len;
-    @panic("TODO");
 }
diff --git a/src/hal/clocks/gclk.zig b/src/hal/clocks/gclk.zig
@@ -63,8 +63,8 @@ pub fn wait_for_sync_mask(mask: u12) void {
 }
 
 pub const EnableGeneratorOptions = struct {
-    divsel: microzig.chip.types.peripherals.GCLK.GCLK_GENCTRL__DIVSEL,
-    div: u16,
+    divsel: microzig.chip.types.peripherals.GCLK.GCLK_GENCTRL__DIVSEL = .DIV1,
+    div: u16 = 1,
 };
 
 pub fn enable_generator(gen: Generator, source: Source, opts: EnableGeneratorOptions) void {