GitHub - a112r/RISC-Machine

Used Verilog to create a fully-functioning 32 bit CPU and Datapath that decodes ARM Assembly instructions and executes them completely on a DE1-SOC FPGA.
Executed extensive coding in System verilog synthesized with Quartus and created extensive test benches to verify the functioning of each and every feature in the project using Modelsim

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
RAM.sv		RAM.sv
README.md		README.md
alu.sv		alu.sv
cpu.sv		cpu.sv
cpu_tb.sv		cpu_tb.sv
data.txt		data.txt
datapath.sv		datapath.sv
datapath_tb.sv		datapath_tb.sv
module_top.sv		module_top.sv
regfile.sv		regfile.sv
shifter.sv		shifter.sv

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