UNRATIFIED RISC-V: Add supervisor counter delegation extensions

[DO NOT MERGE]
Until the Supervisor Counter Delegation Architecture Extension is frozen /
ratified and final version number is determined, this patch should not be
merged upstream. This commit uses version 0.1 as a placeholder because
there's no version number in the current documentation.

This commit adds support for two extensions from the Supervisor Counter
Delegation Architecture Extension specification ('Smcdeleg' and 'Ssccfg')
based on the latest documentation (as of 2023-08-07):
<https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add related implications
	including the ones to 'Zicsr' for compatibility and excluding
	the ones to counter extensions that require *either* 'Zicntr' or
	'Zihpm'.
	(riscv_supported_std_s_ext): Add 'Smcdeleg' and 'Ssccfg' extensions
	to the supported 'S' extension list.
	(riscv_parse_check_conflicts): Check existence of either 'Zicntr' or
	'Zihpm' if either 'Smcdeleg' or 'Ssccfg' is enabled.

bfd/elfxx-riscv.c

@@ -1222,10 +1222,14 @@ static riscv_implicit_subset_t riscv_implicit_subsets[] =
   {"zicntr", "zicsr",	check_implicit_compat_counter_to_zicsr},
   {"zihpm", "zicsr",	check_implicit_compat_counter_to_zicsr},
   {"smaia", "ssaia",		check_implicit_always},
+  {"smcdeleg", "zicsr",		check_implicit_always}, /* Compat.  */
+  {"smcdeleg", "sscrind",	check_implicit_always},
   {"smcsrind", "zicsr",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
+  {"ssccfg", "zicsr",		check_implicit_always}, /* Compat.  */
+  {"ssccfg", "sscrind",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"sscsrind", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
@@ -1376,10 +1380,12 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smcdeleg",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"smcsrind",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ssccfg",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscsrind",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2025,6 +2031,24 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
       no_conflict = false;
     }
 
+  bool support_counters = (riscv_subset_supports (rps, "zicntr")
+			   || riscv_subset_supports (rps, "zihpm"));
+  if (!support_counters)
+    {
+      if (riscv_subset_supports(rps, "smcdeleg"))
+	{
+	  rps->error_handler
+	    (_("`smcdeleg' requires either `zicntr' or `zihpm' extension"));
+	  no_conflict = false;
+	}
+      if (riscv_subset_supports(rps, "ssccfg"))
+	{
+	  rps->error_handler
+	    (_("`ssccfg' requires either `zicntr' or `zihpm' extension"));
+	  no_conflict = false;
+	}
+    }
+
   bool support_zve = false;
   bool support_zvl = false;
   riscv_subset_t *s = rps->subset_list->head;