RISC-V: Add tentative 'Zicntr' and 'Zihpm' support

This commit adds tentative support for 'Zicntr' and 'Zihpm' extensions.
It is designed NOT to emit existence of 'Zicntr' and 'Zihpm' extensions
to output files unless we specify those extensions with version number
in the "-march" option.  In a sense, those extensions are nearly
transparent on supported ISAs (unless we explicitly touch them).

This makes adopting this commit possible without actual ratification.

bfd/ChangeLog:

	* elfxx-riscv.c (check_implicit_for_counters): New function for
	'Zicntr' -> 'Zicsr' and 'Zihpm' -> 'Zicsr' implications.
	(riscv_implicit_subsets): Add implications for
	those extensions so that current "i" always assume both.
	(riscv_supported_std_z_ext): Add tentative 'Zicntr' and 'Zihpm'
	extensions with undetermined version numbers to prevent arch
	string emitting.
	(riscv_parse_add_subset): Add "zicntr" and "zihpm" to exceptions
	to recognize on older ISAs if there's no version number.
	(riscv_multi_subset_supports): Add support for 'Zicntr'.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	'Zicntr' and 'Zihpm' extensions.
	(riscv_csr_address): Add handling for new CSR classes.
	* testsuite/gas/riscv/march-imply-i.s: Add 'Zicntr' instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Change CSR classes for counter CSRs.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICNTR
	for 'Zicntr' pseudoinstructions.

bfd/elfxx-riscv.c

@@ -1030,6 +1030,16 @@ check_implicit_for_i (const char *implicit ATTRIBUTE_UNUSED,
 	      && subset->minor_version < 1));
 }
 
+/* Add the IMPLICIT only when the version of SUBSET is determined.  */
+
+static bool
+check_implicit_for_counters (const char *implicit ATTRIBUTE_UNUSED,
+		      riscv_subset_t *subset)
+{
+  return (subset->major_version != RISCV_UNKNOWN_VERSION
+	  && subset->minor_version != RISCV_UNKNOWN_VERSION);
+}
+
 /* Record all implicit information for the subsets.  */
 struct riscv_implicit_subset
 {
@@ -1043,6 +1053,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"e", "i",		check_implicit_always},
   {"i", "zicsr",	check_implicit_for_i},
   {"i", "zifencei",	check_implicit_for_i},
+  {"i", "zicntr",	check_implicit_always}, /* Mock.  */
+  {"i", "zihpm",	check_implicit_always}, /* Mock.  */
   {"g", "i",		check_implicit_always},
   {"g", "m",		check_implicit_always},
   {"g", "a",		check_implicit_always},
@@ -1101,6 +1113,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zks", "zbkx",	check_implicit_always},
   {"zks", "zksed",	check_implicit_always},
   {"zks", "zksh",	check_implicit_always},
+  {"zicntr", "zicsr",	check_implicit_for_counters},
+  {"zihpm", "zicsr",	check_implicit_for_counters},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1168,11 +1182,13 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicntr",		ISA_SPEC_CLASS_NONE,		RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Mock.  */
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
+  {"zihpm",		ISA_SPEC_CLASS_NONE,		RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION,  0 }, /* Mock.  */
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -1568,9 +1584,12 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
 	rps->error_handler
 	  (_("x ISA extension `%s' must be set with the versions"),
 	   subset);
-      /* Allow old ISA spec can recognize zicsr and zifencei.  */
+      /* Allow old ISA spec can recognize extensions
+	 effectively split from the base 'I' ISA version 2.2.  */
       else if (strcmp (subset, "zicsr") != 0
-	       && strcmp (subset, "zifencei") != 0)
+	       && strcmp (subset, "zifencei") != 0
+	       && strcmp (subset, "zicntr") != 0
+	       && strcmp (subset, "zihpm") != 0)
 	rps->error_handler
 	  (_("cannot find default versions of the ISA extension `%s'"),
 	   subset);
@@ -2258,6 +2277,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICNTR:
+      return riscv_subset_supports (rps, "zicntr");
     case INSN_CLASS_ZICSR:
       return riscv_subset_supports (rps, "zicsr");
     case INSN_CLASS_ZIFENCEI:
@@ -2407,6 +2428,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICNTR:
+      return "zicntr";
     case INSN_CLASS_ZICSR:
       return "zicsr";
     case INSN_CLASS_ZIFENCEI:

gas/config/tc-riscv.c

@@ -66,6 +66,10 @@ enum riscv_csr_class
 
   CSR_CLASS_I,
   CSR_CLASS_I_32,	/* rv32 only */
+  CSR_CLASS_ZICNTR,	/* basic hardware perf counter */
+  CSR_CLASS_ZICNTR_32,	/* basic hardware perf counter, rv32 only */
+  CSR_CLASS_ZIHPM,	/* additional hardware perf counter */
+  CSR_CLASS_ZIHPM_32,	/* additional hardware perf counter, rv32 only */
   CSR_CLASS_F,		/* f-ext only */
   CSR_CLASS_ZKR,	/* zkr only */
   CSR_CLASS_V,		/* rvv only */
@@ -1028,6 +1032,18 @@ riscv_csr_address (const char *csr_name,
       need_check_version = true;
       extension = "i";
       break;
+    case CSR_CLASS_ZICNTR_32:
+      is_rv32_only = true;
+      /* Fall through.  */
+    case CSR_CLASS_ZICNTR:
+      extension = "zicntr";
+      break;
+    case CSR_CLASS_ZIHPM_32:
+      is_rv32_only = true;
+      /* Fall through.  */
+    case CSR_CLASS_ZIHPM:
+      extension = "zihpm";
+      break;
     case CSR_CLASS_H_32:
       is_rv32_only = true;
       /* Fall through.  */

gas/testsuite/gas/riscv/march-imply-i.s

@@ -22,3 +22,11 @@ target:
 
 	# zifencei
 	fence.i
+
+	# zicntr
+	rdcycle		t0
+	rdtime		t0
+	rdinstret	t0
+	rdcycleh	t0
+	rdtimeh		t0
+	rdinstreth	t0