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RISC-V: Add INSN_DREF to memory read/write instructions #90

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RISC-V: Add INSN_DREF to memory read/write instructions #90

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@a4lg a4lg commented Nov 18, 2022

@a4lg a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from a852c00 to 9404ae4 Compare November 19, 2022 11:57
@a4lg a4lg added the bug Something isn't working label Nov 19, 2022
@a4lg a4lg force-pushed the riscv-opcode-dref branch 13 times, most recently from 89d5460 to b9a94e8 Compare November 26, 2022 00:28
@a4lg a4lg force-pushed the riscv-opcode-dref branch 8 times, most recently from 0cb2f27 to 05fffe5 Compare December 2, 2022 03:27
@a4lg a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from ab20a49 to 6c5011a Compare December 11, 2022 06:32
@a4lg a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from 5138b75 to 9678ebc Compare February 8, 2023 05:34
@a4lg a4lg force-pushed the riscv-opcode-dref branch from 9678ebc to a3325e9 Compare February 15, 2023 04:34
@a4lg a4lg force-pushed the riscv-opcode-dref branch from a3325e9 to 24f8c6f Compare March 1, 2023 10:46
@a4lg a4lg force-pushed the riscv-opcode-dref branch from 24f8c6f to 74129b9 Compare March 16, 2023 03:02
@a4lg a4lg force-pushed the riscv-opcode-dref branch 2 times, most recently from 5e081ad to b364daf Compare August 1, 2023 03:40
@a4lg a4lg force-pushed the riscv-opcode-dref branch 8 times, most recently from 0377525 to acf8586 Compare August 8, 2023 04:11
@a4lg a4lg force-pushed the riscv-opcode-dref branch 3 times, most recently from e268655 to 72a9c3e Compare August 15, 2023 06:37
@a4lg a4lg force-pushed the riscv-opcode-dref branch from 72a9c3e to a9475df Compare August 15, 2023 07:27
@a4lg a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from 70cd561 to 126dbde Compare September 7, 2023 09:35
@a4lg a4lg force-pushed the riscv-opcode-dref branch 2 times, most recently from ab1f0c7 to 292f9f8 Compare October 19, 2023 03:17
@a4lg
RISC-V: Add INSN_DREF to memory read/write instructions
a2ca1a3 
This commit adds INSN_DREF flag (and optional size-related flag) to the
instructions that read/write the memory directly.  It however excludes
cache-related instructions that do synchronization of some sort but
otherwise don't touch the contents of the memory.

INSN_DREF and optional size flag are added to following instructions:

-   "cbo.zero" (from the 'Zicboz' extension)
-   All instructions from following custom extensions:
    -   'XTheadFMemIdx'
    -   'XTheadInt'
    -   'XTheadMemIdx'
    -   'XTheadMemPair'

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add INSN_DREF and optional size
	flag on the instructions directly read/write memory.
@a4lg a4lg force-pushed the riscv-opcode-dref branch from 292f9f8 to a2ca1a3 Compare October 19, 2023 07:01
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